LHLD & SHLD Instructions + Sum of Data Array Program

STEP 1 - EXTRACT (Given Data)

• Number of data values: 10 (0AH)
• Data type: 8-bit each
• Data starting address: 6000H (so 6000H to 6009H)
• Sum storage address: 9500H
• Carry storage address: implied 9501H (next location)

All required data is present.

STEP 2 - SOLVE

Part 1: LHLD and SHLD Instructions

LHLD (Load H-L pair Direct)

A 3-byte instruction that loads the contents of two consecutive memory locations directly into the HL register pair.

Syntax: LHLD address

Operation:

• $L \leftarrow M[address]$
• $H \leftarrow M[address+1]$

Example: LHLD 2200H - if 2200H = 45H and 2201H = 32H, then after execution $L = 45H$, $H = 32H$.

Size: 3 bytes, Machine cycles: 5, T-states: 16

SHLD (Store H-L pair Direct)

A 3-byte instruction that stores the contents of the HL register pair into two consecutive memory locations.

Syntax: SHLD address

Operation:

• $M[address] \leftarrow L$
• $M[address+1] \leftarrow H$

Example: SHLD 2302H - if $H = 32H$, $L = 45H$, then 2302H = 45H, 2303H = 32H.

Size: 3 bytes, Machine cycles: 5, T-states: 16

Part 2: Assembly Language Program

Algorithm

1. Initialize carry register $C = 00H$
2. Initialize counter $B = 0AH$ (10 items)
3. Point HL to 6000H
4. Clear accumulator ($A = 00H$)
5. Add memory content to A; if carry occurs, increment C
6. Advance pointer, decrement counter, repeat until zero
7. Store sum at 9500H, carry at 9501H

Program

; Sum of 10 eight-bit data stored from 6000H
; Sum -> 9500H, Carry -> 9501H

        MVI C, 00H      ; carry counter = 0
        MVI B, 0AH      ; counter = 10
        LXI H, 6000H    ; HL points to first data
        SUB A           ; A = 0 (clear accumulator, clears CY)

BACK:   ADD M           ; A = A + [HL]
        JNC SKIP        ; if no carry, skip
        INR C           ; else increment carry register

SKIP:   INX H           ; next memory location
        DCR B           ; decrement counter
        JNZ BACK        ; repeat until counter = 0

        STA 9500H       ; store sum
        MOV A, C        ; move carry to A
        STA 9501H       ; store carry

        HLT             ; halt

Explanation

Key Points

• Register C accumulates the number of carries, forming the high byte of the 16-bit result. Since each byte is at most FFH, the maximum sum of 10 bytes is $10 \times 255 = 2550 = 09F6H$, so C never exceeds 09H: a single carry register suffices.
• SUB A clears the accumulator and also resets the carry flag before the loop.

Result: Low byte of sum stored at 9500H, carry (high byte) stored at 9501H.

Note: the problem does not explicitly state 9501H for the carry, but "starting from 9500H" naturally implies the next byte (9501H), so that assumption is reasonable and standard.

An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions that a microprocessor supports is called the Instruction Set. The 8085 has 246 instructions, each repres...

--- Basis Instruction Cycle Machine Cycle --------- Definition Time required to fetch and execute an entire instruction Time required to access memory or I/O device once Composition Consists of one or more machine cycles Consists of 3 to...

--- Feature 8085 Microprocessor 8086 Microprocessor --------- Data Bus Width 8-bit data bus 16-bit data bus Address Bus Width 16-bit address bus 20-bit address bus Addressable Memory 2^16 = 64 KB 2^20 = 1 MB Word Size 8-bit (processes 8 ...

Direct Memory Access (DMA) - Importance and Mechanism

Importance of Direct Memory Access

Direct Memory Access (DMA) is a technique that allows external I/O devices to communicate directly with the memory without involving the processor every time. Its importance includes:

1. Frees the CPU: The CPU does not need to supervise every data transfer between I/O devices and memory, allowing it to perform other tasks simultaneously.
2. High Speed Data Transfer: Large blocks of data can be transferred at high speed directly between memory and peripherals (e.g., disk drives, network cards) without CPU intervention.
3. Reduced CPU Overhead: Since the CPU is not busy handling each byte of data transfer, overall system performance and efficiency is greatly improved.
4. Efficient Use of System Resources: The processor and I/O operations can proceed in parallel, making better use of available hardware resources.
5. Essential for High-Bandwidth Devices: Devices such as hard disks, graphics cards, and sound cards require fast bulk data transfers that would be too slow if handled byte-by-byte by the CPU.

Mechanism of Direct Memory Access

The DMA mechanism works through a dedicated hardware unit called the DMA Controller (DMAC). The steps involved are as follows:

Step 1: DMA Request

• When an I/O device needs to transfer data to/from memory, it sends a DMA request signal to the DMA controller.

Step 2: HOLD Signal to CPU

• The DMA controller activates the HOLD pin of the microprocessor.
• This signals the CPU to relinquish (release) control of the system buses (address bus, data bus, and control bus).

Step 3: HLDA (Hold Acknowledge)

• The CPU completes its current bus cycle and then sends a Hold Acknowledge (HLDA) signal back to the DMA controller.
• The CPU now enters a hold state and stops using the buses.

Step 4: DMA Takes Control of Buses

• The DMA controller now takes control of:
  • Address Bus - to specify memory locations
  • Data Bus - to transfer data
  • Control Bus - to generate read/write signals

Step 5: Data Transfer

• The DMA controller directly transfers data between the I/O device and memory without CPU involvement.
• This transfer can be:
  • Byte by byte (cycle stealing mode)
  • Block transfer (burst mode)

Step 6: Release of Buses

• After the data transfer is complete, the DMA controller deactivates the HOLD signal.
• The CPU regains control of the buses and resumes normal operation.

DMA Transfer Diagram

I/O Device  ---[DMA Request]---> DMA Controller
                                      |
                               [HOLD Signal]
                                      |
                               Microprocessor
                                      |
                              [HLDA - Acknowledge]
                                      |
DMA Controller takes Address, Data, Control Buses
                                      |
         Direct Transfer: I/O Device <-----> Memory
                                      |
                         DMA releases buses
                                      |
                         CPU resumes operation

Summary

DMA is important because it enables fast, CPU-independent data transfer between memory and peripherals. The mechanism relies on the HOLD and HLDA handshake between the DMA controller and the CPU, after which the DMA controller directly manages the buses to perform the transfer efficiently.

LHLD & SHLD Instructions + Sum of Data Array Program

STEP 1 - EXTRACT (Given Data)

• Number of data values: 10 (0AH)
• Data type: 8-bit each
• Data starting address: 6000H (so 6000H to 6009H)
• Sum storage address: 9500H
• Carry storage address: implied 9501H (next location)

All required data is present.

STEP 2 - SOLVE

Part 1: LHLD and SHLD Instructions

LHLD (Load H-L pair Direct)

A 3-byte instruction that loads the contents of two consecutive memory locations directly into the HL register pair.

Syntax: LHLD address

Operation:

• $L \leftarrow M[address]$
• $H \leftarrow M[address+1]$

Example: LHLD 2200H - if 2200H = 45H and 2201H = 32H, then after execution $L = 45H$, $H = 32H$.

Size: 3 bytes, Machine cycles: 5, T-states: 16

SHLD (Store H-L pair Direct)

A 3-byte instruction that stores the contents of the HL register pair into two consecutive memory locations.

Syntax: SHLD address

Operation:

• $M[address] \leftarrow L$
• $M[address+1] \leftarrow H$

Example: SHLD 2302H - if $H = 32H$, $L = 45H$, then 2302H = 45H, 2303H = 32H.

Size: 3 bytes, Machine cycles: 5, T-states: 16

Part 2: Assembly Language Program

Algorithm

1. Initialize carry register $C = 00H$
2. Initialize counter $B = 0AH$ (10 items)
3. Point HL to 6000H
4. Clear accumulator ($A = 00H$)
5. Add memory content to A; if carry occurs, increment C
6. Advance pointer, decrement counter, repeat until zero
7. Store sum at 9500H, carry at 9501H

Program

; Sum of 10 eight-bit data stored from 6000H
; Sum -> 9500H, Carry -> 9501H

        MVI C, 00H      ; carry counter = 0
        MVI B, 0AH      ; counter = 10
        LXI H, 6000H    ; HL points to first data
        SUB A           ; A = 0 (clear accumulator, clears CY)

BACK:   ADD M           ; A = A + [HL]
        JNC SKIP        ; if no carry, skip
        INR C           ; else increment carry register

SKIP:   INX H           ; next memory location
        DCR B           ; decrement counter
        JNZ BACK        ; repeat until counter = 0

        STA 9500H       ; store sum
        MOV A, C        ; move carry to A
        STA 9501H       ; store carry

        HLT             ; halt

Explanation

Key Points

• Register C accumulates the number of carries, forming the high byte of the 16-bit result. Since each byte is at most FFH, the maximum sum of 10 bytes is $10 \times 255 = 2550 = 09F6H$, so C never exceeds 09H: a single carry register suffices.
• SUB A clears the accumulator and also resets the carry flag before the loop.

Result: Low byte of sum stored at 9500H, carry (high byte) stored at 9501H.

Note: the problem does not explicitly state 9501H for the carry, but "starting from 9500H" naturally implies the next byte (9501H), so that assumption is reasonable and standard.

An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions that a microprocessor supports is called the Instruction Set. The 8085 has 246 instructions, each repres...

--- Basis Instruction Cycle Machine Cycle --------- Definition Time required to fetch and execute an entire instruction Time required to access memory or I/O device once Composition Consists of one or more machine cycles Consists of 3 to...

--- Feature 8085 Microprocessor 8086 Microprocessor --------- Data Bus Width 8-bit data bus 16-bit data bus Address Bus Width 16-bit address bus 20-bit address bus Addressable Memory 2^16 = 64 KB 2^20 = 1 MB Word Size 8-bit (processes 8 ...

Direct Memory Access (DMA) - Importance and Mechanism

Importance of Direct Memory Access

Direct Memory Access (DMA) is a technique that allows external I/O devices to communicate directly with the memory without involving the processor every time. Its importance includes:

1. Frees the CPU: The CPU does not need to supervise every data transfer between I/O devices and memory, allowing it to perform other tasks simultaneously.
2. High Speed Data Transfer: Large blocks of data can be transferred at high speed directly between memory and peripherals (e.g., disk drives, network cards) without CPU intervention.
3. Reduced CPU Overhead: Since the CPU is not busy handling each byte of data transfer, overall system performance and efficiency is greatly improved.
4. Efficient Use of System Resources: The processor and I/O operations can proceed in parallel, making better use of available hardware resources.
5. Essential for High-Bandwidth Devices: Devices such as hard disks, graphics cards, and sound cards require fast bulk data transfers that would be too slow if handled byte-by-byte by the CPU.

Mechanism of Direct Memory Access

The DMA mechanism works through a dedicated hardware unit called the DMA Controller (DMAC). The steps involved are as follows:

Step 1: DMA Request

• When an I/O device needs to transfer data to/from memory, it sends a DMA request signal to the DMA controller.

Step 2: HOLD Signal to CPU

• The DMA controller activates the HOLD pin of the microprocessor.
• This signals the CPU to relinquish (release) control of the system buses (address bus, data bus, and control bus).

Step 3: HLDA (Hold Acknowledge)

• The CPU completes its current bus cycle and then sends a Hold Acknowledge (HLDA) signal back to the DMA controller.
• The CPU now enters a hold state and stops using the buses.

Step 4: DMA Takes Control of Buses

• The DMA controller now takes control of:
  • Address Bus - to specify memory locations
  • Data Bus - to transfer data
  • Control Bus - to generate read/write signals

Step 5: Data Transfer

• The DMA controller directly transfers data between the I/O device and memory without CPU involvement.
• This transfer can be:
  • Byte by byte (cycle stealing mode)
  • Block transfer (burst mode)

Step 6: Release of Buses

• After the data transfer is complete, the DMA controller deactivates the HOLD signal.
• The CPU regains control of the buses and resumes normal operation.

DMA Transfer Diagram

I/O Device  ---[DMA Request]---> DMA Controller
                                      |
                               [HOLD Signal]
                                      |
                               Microprocessor
                                      |
                              [HLDA - Acknowledge]
                                      |
DMA Controller takes Address, Data, Control Buses
                                      |
         Direct Transfer: I/O Device <-----> Memory
                                      |
                         DMA releases buses
                                      |
                         CPU resumes operation

Summary

DMA is important because it enables fast, CPU-independent data transfer between memory and peripherals. The mechanism relies on the HOLD and HLDA handshake between the DMA controller and the CPU, after which the DMA controller directly manages the buses to perform the transfer efficiently.

Register Organization in 80386 Microprocessor

Register Organization of 80386 Microprocessor

The Intel 80386 is a 32-bit microprocessor. Its registers are organized into the following groups:

1. General Purpose Registers (32-bit)

These registers are used for arithmetic, logical, and data transfer operations.

• Each 32-bit register can also be accessed as a 16-bit register (AX, BX, CX, DX, SP, BP, SI, DI).
• AX, BX, CX, DX can further be split into 8-bit high and low bytes (AH/AL, BH/BL, CH/CL, DH/DL).

2. Segment Registers (16-bit)

The 80386 uses segmented memory model. It has 6 segment registers:

3. Control Registers

Important flags in EFLAGS:

• CF - Carry Flag
• ZF - Zero Flag
• SF - Sign Flag
• OF - Overflow Flag
• DF - Direction Flag (for string operations)
• IF - Interrupt Enable Flag

4. System Registers

These are used for memory management and protection in protected mode:

Summary Diagram

80386 Registers
├── General Purpose (EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP) -- 32-bit
├── Segment Registers (CS, DS, SS, ES, FS, GS) -- 16-bit
├── Control Registers (EIP, EFLAGS) -- 32-bit
└── System Registers (CR0-CR3, GDTR, LDTR, IDTR, TR)

Key Feature

The 80386 supports backward compatibility - programs written for 8086/80286 can run on 80386 because the lower 16-bit portions of the registers (AX, BX, etc.) are preserved within the 32-bit extended registers (EAX, EBX, etc.).

The Intel 80286 is a 16-bit microprocessor introduced by Intel in 1982. It is an advanced version of the 8086/8088 microprocessors. It has a 16-bit data bus and a 24-bit address bus, which allows it to address up to 16 MB of physical mem...

An addressing mode refers to the way in which the operand (data) of an instruction is specified. The 8085 microprocessor supports 5 types of addressing modes. --- - In this mode, the data (operand) is directly specified in the instructio...

Limitations of Parallel Communication and Operation Modes of 8255A PPI

Part 1: Limitations of Parallel Communication

Parallel communication transmits multiple bits simultaneously over multiple lines, but it has the following limitations:

1. Cost: Requires more wires/lines (one for each bit), making it more expensive than serial communication.
2. Distance Limitation: Suitable only for short distances (typically within a few meters) because signal degradation and crosstalk increase with distance.
3. Crosstalk: Interference between adjacent parallel lines causes data errors, especially at high speeds over longer distances.
4. Synchronization Problem: All bits must arrive at the same time; skew (timing differences between lines) can cause data corruption.
5. Cable Bulk: Multiple wires make the cable thick, heavy, and difficult to manage.
6. Higher Power Consumption: More lines mean more drivers and receivers, consuming more power.
7. Not Suitable for Long Distance: Cannot be used effectively for long-distance communication unlike serial communication.

Part 2: Operation Modes of 8255A PPI

The 8255A Programmable Peripheral Interface (PPI) has three ports: Port A, Port B, and Port C. It operates in the following modes, determined by the Control Word Register (bit D7 = 1 for I/O mode):

Mode 0: Basic Input/Output Mode

• This is the simplest mode of operation.
• Port A, Port B, and both halves of Port C (upper and lower) can be independently configured as input or output.
• No handshaking signals are required.
• Data is simply written to or read from the ports.
• Suitable for simple I/O operations like reading switches or driving LEDs.
• Port C can be split: upper nibble (PC7-PC4) and lower nibble (PC3-PC0) configured separately.

Example use: Connecting keyboards, displays, or simple peripheral devices.

Mode 1: Strobed Input/Output Mode (Handshaking Mode)

• Used for Port A and Port B only.
• Port C lines are used as handshaking/control signals for Port A and Port B.
• Data transfer occurs with synchronization signals (handshaking).
• Two sub-modes:
  • Mode 1 Input: Uses signals like STB (Strobe), IBF (Input Buffer Full), and INTR (Interrupt Request).
  • Mode 1 Output: Uses signals like OBF (Output Buffer Full), ACK (Acknowledge), and INTR.
• Suitable when the peripheral needs to signal readiness before data transfer.

Example use: Interfacing with printers or other devices requiring handshaking.

Mode 2: Bidirectional Bus Mode

• Available for Port A only.
• Port A acts as a bidirectional 8-bit data bus (both input and output on the same port).
• Port C lines (PC7-PC3) are used as control/handshaking signals for Port A.
• Port B can still operate in Mode 0 or Mode 1 independently.
• Suitable for communication between two microprocessors or complex peripherals.

Example use: Data transfer between two CPUs sharing a common bus.

Bit Set/Reset (BSR) Mode

• This is a special mode for Port C only.
• When bit D7 = 0 in the control word, Port C operates in BSR mode.
• Individual bits of Port C can be set (1) or reset (0) using a specific control word.
• This does not affect Port A or Port B operations.
• Useful for generating control signals or flags on individual pins.

Summary Table

Vectored Interrupt, Maskable and Non-Maskable Interrupts in 8085

Vectored Interrupt

A vectored interrupt is an interrupt in which the interrupting device not only signals the processor for attention but also identifies itself by providing the address (vector) of its Interrupt Service Routine (ISR) directly.

• When a vectored interrupt occurs, the microprocessor automatically jumps to a fixed, pre-defined memory address associated with that interrupt, without needing to poll or search for the source.
• This makes the response faster and more efficient.

Example: In the 8085, interrupts like TRAP, RST 5.5, RST 6.5, RST 7.5 are vectored interrupts because each one has a fixed call address in memory.

In contrast, a non-vectored interrupt (like INTR) does not provide the address directly; the processor must determine the ISR address through external hardware.

Interrupts in 8085 Microprocessor

The 8085 has 5 hardware interrupt pins:

1. Maskable Interrupts

• A maskable interrupt is one that can be enabled or disabled (masked) by the programmer using software instructions.
• In 8085, the EI (Enable Interrupt) and DI (Disable Interrupt) instructions are used to enable or disable maskable interrupts.
• When the processor is busy with a critical task, it can ignore (mask) these interrupts temporarily.
• The response to a maskable interrupt can be immediate or delayed.

Maskable interrupts in 8085:

• INTR - General purpose maskable interrupt; requires external hardware to supply the restart address.
• RST 5.5 - Vectored; calls address 002CH
• RST 6.5 - Vectored; calls address 0034H
• RST 7.5 - Vectored; calls address 003CH (highest priority among maskable)

These can also be individually masked using the SIM (Set Interrupt Mask) instruction.

2. Non-Maskable Interrupt

• A non-maskable interrupt is one that cannot be disabled or ignored by the programmer. The processor must respond to it immediately regardless of the state of the interrupt enable flag.
• It is used for emergency or critical situations such as power failure.

Non-maskable interrupt in 8085:

• TRAP - It is the only non-maskable interrupt in 8085.
  • It has the highest priority among all interrupts.
  • It is both edge-triggered and level-triggered (making it very reliable).
  • It calls the fixed address 0024H.
  • It cannot be masked by EI/DI instructions or SIM instruction.

Summary Table

Short Notes: Flags in 8085 MPU and DMA

a. Flags in 8085 MPU

Flags are special flip-flop circuits within the Flag Register (also called the Program Status Word) of the 8085 microprocessor. They are set (1) or reset (0) automatically based on the result of arithmetic and logical operations performed by the ALU. They indicate the status of the accumulator and other registers after the completion of an operation.

The 8085 MPU uses 5 flags, arranged in an 8-bit flag register:

The Five Flags:

1. Sign Flag (S)

   • Set to 1 if the result of an operation is negative (i.e., the MSB/D7 bit of the result is 1).
   • Reset to 0 if the result is positive.

2. Zero Flag (Z)

   • Set to 1 if the result of an operation is zero.
   • Reset to 0 if the result is non-zero.

3. Auxiliary Carry Flag (AC)

   • Set to 1 if there is a carry out from bit D3 to bit D4 (carry from the lower nibble to the upper nibble).
   • Primarily used in BCD (Binary Coded Decimal) arithmetic operations.

4. Parity Flag (P)

   • Set to 1 if the result contains an even number of 1s (even parity).
   • Reset to 0 if the result contains an odd number of 1s (odd parity).

5. Carry Flag (CY)

   • Set to 1 if an arithmetic operation generates a carry out from the MSB (D7) or requires a borrow.
   • Used in multi-byte addition and subtraction operations.

These flags are essential for conditional branching instructions (e.g., JZ, JNZ, JC, JNC) which allow the program to make decisions based on the result of previous operations.

b. DMA (Direct Memory Access)

DMA (Direct Memory Access) is a technique that allows I/O devices to transfer data directly to or from memory without the involvement of the CPU for each byte of data transferred.

Need for DMA:

• Normally, data transfer between memory and I/O devices is managed by the CPU, which wastes CPU time.
• For large and high-speed data transfers (e.g., disk drives, video, network), DMA provides a much faster and efficient method.

How DMA Works:

1. The I/O device requests a DMA transfer by sending a signal to the DMA Controller (DMAC).
2. The DMAC sends a HOLD request to the CPU.
3. The CPU completes its current operation, then sends a HLDA (Hold Acknowledge) signal and releases the buses (address, data, and control buses).
4. The DMAC takes control of the buses and transfers data directly between the I/O device and memory.
5. After the transfer is complete, the DMAC releases the buses and the CPU resumes normal operation.

Key Components:

• DMA Controller (DMAC): A dedicated chip (e.g., Intel 8257) that manages the transfer.
• HOLD and HLDA pins of the 8085 are used for DMA handshaking.

Advantages of DMA:

• Fast data transfer at memory speed.
• CPU is free to perform other tasks (or is only briefly paused).
• Efficient for bulk data transfers.

Disadvantage:

• Requires additional hardware (DMAC chip), increasing system cost and complexity.

Summary Table:

--- An addressing mode refers to the way in which the operand (data) of an instruction is specified. The 8086 microprocessor supports the following addressing modes: --- - The operand (data) is directly specified in the instruction itsel...

In Protected Mode of the 80286/80386 microprocessor, memory access is managed through a structure called the Global Descriptor Table (GDT). The segment registers no longer hold base addresses directly; instead, they hold selectors that p...

--- Ports are the interfaces through which the CPU communicates with external devices. The main types of ports are: - Used to transfer data from peripheral devices to the CPU. - Example: Keyboard port, scanner port. - Used to transfer da...

A bus is a group of conducting wires (lines) that connects different components of a computer system (CPU, memory, and I/O devices) and carries information between them. There are three types of system buses: --- - A group of conducting ...