Common Bus System in Computer Architecture with Diagram: Registers, Selection Table, Answer

"Explain the common bus system with a diagram" is a standard question from the Basic Computer Organization and Design unit of TU BSc CSIT Computer Architecture (CSC213, unit 3), and from Simple Computer Architecture Models in BIT151 Microprocessor and Computer Architecture (unit 6). The textbook machine behind it is Mano's basic computer, which connects its registers and memory through one shared 16-bit path.

This article explains what the common bus is, why a basic computer uses a bus instead of direct paths between registers, how the selection lines S2 S1 S0 choose the source, and how LD, INR and CLR choose the destinations. It includes the selection table, the register size table and a 10-mark answer outline. The unit notes are on the Basic Computer Organization and Design notes page.

What is a common bus system

A common bus is a set of wires shared by several registers and the memory, so that data can travel from any one of them to any other over the same lines. In the basic computer the bus is 16 bits wide. At any instant exactly one unit places its contents on the bus (the source), and one or more registers can copy that value in (the destinations). The transfer is controlled by a multiplexer that picks the source and by load signals that pick the destinations.

Without a bus, every register that must send data to another would need its own set of wires to it. With 8 registers that quickly becomes a tangle of point-to-point paths, one multiplexer at every register input, and a lot of wiring. A bus replaces this with one set of wires and one selector.

Registers connected to the bus

The basic computer has eight registers and a 4096 x 16 memory. Their sizes follow from the address and word lengths: an address is 12 bits (4096 words) and every word, instruction and data value is 16 bits.

AR and PC are 12 bits, so when they drive the 16-bit bus only the low-order 12 lines carry their value and the upper four lines are zero. INPR and OUTR are 8 bits and connect to the accumulator side rather than being selected as bus sources: INPR feeds the accumulator through its adder and logic circuit, and OUTR loads from the low 8 bits of the bus.

Selection lines S2 S1 S0

The bus has seven possible sources (AR, PC, DR, AC, IR, TR and memory), so a 3-bit code on S2 S1 S0 is enough to choose one of them. Each of the 16 bit positions has its own multiplexer, and all of them share the same three select lines.

The control unit generates S2 S1 S0 from the timing signals and decoded instruction. For example, S2 S1 S0 = 010 puts PC on the bus, and 111 puts the memory word addressed by AR on the bus.

Controlling the destinations: LD, INR, CLR

Selecting a source does nothing until a destination register is told to take the value. Each register has three control inputs:

Because only a register whose LD is enabled accepts the bus value, several registers can be connected to the same bus lines without interfering with one another. The memory has two control signals: read puts the addressed word on the bus when S2 S1 S0 = 111, and write stores the value on the bus into the addressed location.

A transfer on the bus

The fetch phase of the instruction cycle shows the bus in use. The notation is register transfer language, where the part before the comma is the timing condition.

At timing signal $T_0$ the address of the next instruction is moved to AR. The control unit sets S2 S1 S0 = 010 so PC drives the bus, and enables LD of AR:

$$T_0:; AR \leftarrow PC$$

At $T_1$ the instruction is read from memory into IR and PC is incremented. Memory drives the bus (S2 S1 S0 = 111), LD of IR is enabled, and INR of PC is enabled in the same pulse:

$$T_1:; IR \leftarrow M[AR],; PC \leftarrow PC + 1$$

At $T_2$ the address field of the instruction is moved back to AR. IR drives the bus (S2 S1 S0 = 101) and LD of AR is enabled:

$$T_2:; AR \leftarrow IR(0\text{-}11)$$

Only one source is on the bus at a time, which is why PC to AR and memory to IR happen in separate clock periods. The one exception is the increment of PC at $T_1$, because INR does not use the bus at all.

Why use a bus instead of direct paths

A bus is chosen because it trades a little speed for a large saving in hardware.

The limitation is the last row: a bus allows one transfer at a time, so operations that could overlap with direct paths must be ordered over several clock pulses. Larger machines add more than one bus to reduce this bottleneck.

How to write it in the exam

For a 10-mark question, a good outline is: (1) define a common bus and say it is 16 bits wide; (2) draw the diagram with the eight registers, memory, the selection multiplexer, and the S2 S1 S0 lines; (3) give the selection table; (4) explain LD, INR and CLR as the destination controls; (5) give the fetch example $AR \leftarrow PC$ with the control signals used; (6) end with advantages (less wiring, cheap) and the limitation (one transfer at a time). For 5 marks, the definition, diagram and selection table are enough.

CSIT students can revisit the preceding unit on Register Transfer and Microoperations, which introduces the transfer notation used above, and practise past questions on the CSC213 Computer Architecture page. BIT students will find the same machine under Simple Computer Architecture Models in BIT151.