Clocked RS Flip Flop Truth Table and Mod 3, Mod 5 Synchronous Counter Design: Digital Logic

Flip-flop truth tables and counter design make up a large share of the sequential logic questions in TU BSc CSIT Digital Logic (CSC116), units 6 and 7 (Synchronous and Asynchronous Sequential Logic, and Registers and Counters), and in BIT103 Digital Logic, units 8 and 9 (Flip-Flops and Latches, and Sequential Circuits and Counters). The combinational neighbours of those questions, the half subtractor, the full adder built from a decoder, and multiplexer against demultiplexer, come from the combinational units (CSC116 units 4 and 5, BIT103 units 5 and 6).

This article collects the clocked RS flip-flop truth table with the D, JK and T tables, the T excitation table, a full design of a mod-5 synchronous counter using T flip-flops (with the mod-3 variant), a binary ripple counter and a 2-bit asynchronous counter using D flip-flops, the half subtractor, a full adder using a 3-to-8 decoder, and a MUX and DEMUX comparison. The unit notes are on the Synchronous and Asynchronous Sequential Logic notes page.

Clocked RS flip-flop truth table

A clocked RS flip-flop is an SR latch with a gating stage: the inputs S and R affect the output only while the clock is 1. When the clock is 0 the flip-flop holds its state. Q is the present state and $Q^+$ the next state after the clock pulse.

The characteristic equation is $Q^+ = S + R'Q$ with the constraint $SR = 0$. The invalid row is what the other three flip-flops are designed to avoid.

D, JK and T flip-flop tables

All tables below are for CLK = 1, the active clock condition.

The characteristic equations are $Q^+ = D$, $Q^+ = JQ' + K'Q$ and $Q^+ = T \oplus Q$. The D flip-flop passes its input to the output, the JK flip-flop removes the invalid state of the RS by toggling when J = K = 1, and the T flip-flop toggles whenever T = 1.

For design, the excitation table lists the input needed for each required transition. For the T flip-flop it is:

T = 1 exactly when the state has to change, which makes T flip-flop designs short.

Mod-5 synchronous counter using T flip-flops

A mod-5 counter goes through five states and then returns to the first: 000, 001, 010, 011, 100, then 000. The smallest n with $2^n \ge 5$ is 3, so three T flip-flops $Q_2 Q_1 Q_0$ on a common clock are needed. The states 101, 110 and 111 never occur and are treated as don't-cares.

The state table, with the T inputs found from the excitation table (T = 1 wherever a bit changes), is:

Plotting each T column on a 3-variable K-map and grouping the 1s together with the don't-cares gives the simplified results. For $T_0$ the ones are in the four rows with $Q_2 = 0$, so $T_0 = Q_2'$. For $T_1$ the ones are at 001 and 011, and with don't-cares at 101 and 111 they form the group $Q_0 = 1$, so $T_1 = Q_0$. For $T_2$ the ones are at 011 and 100, which are covered by $Q_1 Q_0$ and by $Q_2$ with the don't-cares:

$$T_0 = Q_2'$$

$$T_1 = Q_0$$

$$T_2 = Q_2 + Q_1 Q_0$$

The circuit is three T flip-flops on one clock with an inverter, an AND gate and an OR gate. Check the result by tracing: from 011, $T_2 = 1$, $T_1 = 1$, $T_0 = 1$, so all three bits toggle and the state becomes 100; from 100, $T_2 = 1$ and the others are 0, so $Q_2$ toggles to 0 and the state becomes 000. The unused states are self-correcting: 101 goes to 011, 110 goes to 010, and 111 goes to 001, each of which is a valid state.

Mod-3 synchronous counter

A mod-3 counter needs two flip-flops and counts 00, 01, 10 and back to 00, with 11 as the don't-care. Using T flip-flops, the transition 00 to 01 needs $T_1 T_0 = 01$, 01 to 10 needs $11$, and 10 to 00 needs $10$. The K-maps give

$$T_0 = Q_1'$$

$$T_1 = Q_1 + Q_0$$

Binary ripple counter and 2-bit asynchronous counter using D flip-flops

A binary ripple counter is an asynchronous counter in which each flip-flop is clocked by the output of the previous one. An n-bit ripple counter counts from 0 to $2^n - 1$ and is a mod-$2^n$ counter, and its total delay is n times the delay of one flip-flop.

A D flip-flop is turned into a toggle flip-flop by connecting its D input to its own Q' output, because then $Q^+ = D = Q'$ at every clock edge. For a 2-bit asynchronous counter with positive-edge-triggered D flip-flops, FF0 has $D_0 = Q_0'$ and is clocked by the external clock. FF1 has $D_1 = Q_1'$ and is clocked by $Q_0'$, so FF1 toggles when $Q_0$ falls from 1 to 0. The output sequence $Q_1 Q_0$ is

If FF1 is clocked from $Q_0$ instead, the circuit counts down: 00, 11, 10, 01. The diagram below shows the same wiring drawn with T flip-flops, which behave exactly like D flip-flops tied to Q'.

Half subtractor truth table

A half subtractor subtracts one bit B from another bit A and produces a difference D and a borrow Bo.

The equations read directly from the table are

$$D = A'B + AB' = A \oplus B$$

$$Bo = A'B$$

so the circuit is one XOR gate and one AND gate with an inverter on A.

Full adder using a 3-to-8 decoder

A full adder adds A, B and a carry-in $C_{in}$. Its truth table gives the sum 1 for the input combinations with an odd number of ones, and the carry 1 when at least two inputs are 1. In minterm form, with the inputs taken as A B $C_{in}$,

$$S = \Sigma m(1, 2, 4, 7)$$

$$C_{out} = \Sigma m(3, 5, 6, 7)$$

A 3-to-8 decoder generates all eight minterms $m_0$ to $m_7$ from the three inputs, one output line per minterm. The full adder is built by feeding A, B and $C_{in}$ to the decoder, connecting outputs 1, 2, 4 and 7 to a 4-input OR gate to produce S, and connecting outputs 3, 5, 6 and 7 to another 4-input OR gate to produce $C_{out}$. Minterm 7 is shared by both OR gates.

Multiplexer and demultiplexer

A DEMUX with the data input held at 1 is the same as a decoder, which is why decoders are used to build the adder above.

How to write it in the exam

For a design question, write the number of flip-flops, the state table with the excitation columns, the K-map equations and a neat circuit, then verify one or two transitions. For a truth-table question, give the table, the characteristic equation and one line on the behaviour.

Related notes for BIT students are Flip-Flops and Latches and Sequential Circuits and Counters, and CSIT students can continue with Registers and Counters. Past questions for the whole subject are on the CSC116 Digital Logic page.