Synchronous vs Asynchronous Counters: Difference Table, Working and Design for Digital Logic Exams

"Differentiate between synchronous and asynchronous counters" is a fixture of the Registers and Counters unit in TU BSc CSIT Digital Logic (CSC116) and the Sequential Circuits and Counters unit in BIT Digital Logic (BIT103). It appears as a 5-mark comparison on its own and as half of a 10-mark question that also asks you to design a specific counter.

This article explains how each type works, gives the comparison table in the form examiners expect, and outlines the design of each kind so that the second half of the 10-mark question is covered too. The unit notes and solved past questions are on the Registers and Counters notes page.

What a counter is

A counter is a sequential circuit that goes through a fixed sequence of states when it receives input pulses. It is built from flip-flops, usually T or JK flip-flops wired to toggle, and one flip-flop stores one bit of the count. A counter with n flip-flops has 2^n possible states; a counter that uses all of them is a mod-2^n counter, and one that returns to zero after N states is a mod-N counter.

Counters are classified by how the flip-flops receive the clock. That single difference is what the exam question is about.

Asynchronous (ripple) counter

In an asynchronous counter only the first flip-flop is driven by the external clock. The output of each flip-flop serves as the clock input of the next one. A change therefore ripples through the chain, which is why it is also called a ripple counter.

Take a 4-bit binary up counter made from four negative-edge-triggered T flip-flops, each with T = 1 so it toggles on every falling edge at its clock input. The clock drives flip-flop Q0. Q0's output drives the clock of Q1, Q1 drives Q2, and Q2 drives Q3. Q0 toggles on every clock pulse, Q1 toggles every time Q0 falls from 1 to 0, Q2 every time Q1 falls, and so on. The outputs Q3 Q2 Q1 Q0 read 0000, 0001, 0010 ... 1111 and wrap to 0000, which is a mod-16 counter.

The problem is timing. If each flip-flop takes a propagation delay t_pd to change, then the transition from 0111 to 1000 requires Q0 to fall, then Q1, then Q2, then Q3, so the final bit settles only after 4 t_pd. During that time the outputs pass through wrong intermediate values (0110, 0100, 0000) before reaching 1000. For n flip-flops the worst-case delay is n t_pd, and the maximum clock frequency is limited to about 1 / (n t_pd). Decoding the outputs while they are rippling can produce glitches.

A ripple counter is nevertheless the simplest counter to build: no gates are needed between the flip-flops for a plain binary count.

Synchronous counter

In a synchronous counter every flip-flop receives the same clock pulse at the same time. The flip-flops that are supposed to change on a given pulse are selected by combinational logic on their T or J and K inputs, so all changes happen together, one propagation delay after the clock edge.

For a 4-bit synchronous binary up counter using T flip-flops: T0 = 1 (Q0 toggles every pulse); T1 = Q0 (Q1 toggles when Q0 is 1); T2 = Q0 Q1; T3 = Q0 Q1 Q2. Each flip-flop toggles when all lower bits are 1, which is exactly the rule for binary counting. The AND gates that produce these conditions are the price of synchronous operation.

Because every output settles after a single t_pd regardless of the number of bits, the synchronous counter can run at a much higher clock frequency, and the outputs never show intermediate wrong states. It is also far easier to design a synchronous counter for an arbitrary sequence, such as a mod-6 or a BCD counter, because the design is a standard state-table procedure.

Comparison table

If the question says "with a diagram", draw the 4-bit versions of both: a chain of four flip-flops with Q of each feeding the clock of the next for the ripple counter, and four flip-flops on a common clock line with the three AND gates for the synchronous one.

Designing a synchronous mod-N counter

The 10-mark question usually ends with "design a synchronous mod-6 counter using JK flip-flops" or a similar sequence. The procedure is the same every time:

1. Decide the number of flip-flops: the smallest n with 2^n >= N. For mod-6, n = 3.
2. Write the state table: present state Q2 Q1 Q0 and next state. For mod-6 it counts 000, 001, 010, 011, 100, 101 and returns to 000.
3. Using the JK excitation table (0 to 0: J = 0, K = X; 0 to 1: J = 1, K = X; 1 to 0: J = X, K = 1; 1 to 1: J = X, K = 0), fill in the required J and K for each flip-flop in each row.
4. Simplify each J and K input with a K-map, treating the unused states 110 and 111 as don't-cares.
5. Draw the circuit: three JK flip-flops on a common clock with the simplified logic on their inputs.

For the mod-6 counter the results are J0 = K0 = 1; J1 = Q2' Q0 with K1 = Q0; J2 = Q1 Q0 with K2 = Q0. The Q2' term in J1 is the one students miss: without it, state 101 would set Q1 and the counter would go to 110 instead of 000. Verify by tracing the sequence through all six states; also check that the unused states 110 and 111 lead back into the valid sequence (here 110 goes to 111 and 111 goes to 000), which is called self-correction.

Designing an asynchronous mod-N counter

A ripple counter for a non-power-of-two modulus is built by letting a mod-2^n ripple counter run and detecting the state N with a NAND gate that drives the asynchronous clear inputs of all flip-flops. For a mod-6 ripple counter: three flip-flops count 000 to 111; a NAND gate on Q2 and Q1 goes low the instant the count reaches 110, clearing the counter to 000. The state 110 exists only for a few nanoseconds, which is another reason ripple counters are avoided when the outputs must be clean.

Up, down and up-down

Both types can count down. In a ripple down counter the complement output of each stage clocks the next one (or positive-edge-triggered flip-flops are used). In a synchronous down counter the toggle conditions use the complemented outputs: T1 = Q0', T2 = Q0' Q1', and so on. An up-down counter adds a mode input that selects between the two sets of conditions with AND-OR logic.

Answer outline

For 5 marks: define a counter in one sentence, state the one-line difference (clocking), and give the comparison table with six to eight rows. For 10 marks: add the working of both 4-bit counters with diagrams, the propagation delay argument with the n t_pd figure, and the design steps for whichever mod-N counter is asked.

The sequential logic that counters are built on is in the previous unit, Synchronous and Asynchronous Sequential Logic. BIT students find the same topic in Sequential Circuits and Counters in BIT103. Past papers for the full subject are on the CSC116 Digital Logic page.