Design a combinational circuit with three inputs (A, B, C) where the output F = 1 when the binary value of the inputs is odd. --- Signal Description --------------------- A Most Significant Bit (MSB) B Middle Bit C Least Significant Bit ...

Parallel (Synchronous) Counter and MOD-12 Design

Definition of Parallel (Synchronous) Counter

A parallel counter (also called a synchronous counter) is a sequential digital circuit in which all flip-flops receive the clock pulse simultaneously. Unlike ripple (asynchronous) counters where each flip-flop triggers the next, in a synchronous counter the clock is applied in parallel to all flip-flops at the same time.

Key features:

• All flip-flops are clocked simultaneously
• No propagation delay accumulation (faster operation)
• Uses combinational logic (AND gates) to control flip-flop inputs
• Suitable for high-speed applications

MOD-12 Synchronous Up Counter Design

A MOD-12 counter counts from 0 to 11 (0000 to 1011 in binary) and then resets to 0. It requires 4 flip-flops (since 2^4 = 16 > 12).

Step 1: State Diagram

  0000 → 0001 → 0010 → 0011 → 0100 → 0101
    ↑                                      ↓
  1011 ← 1010 ← 1001 ← 1000 ← 0111 ← 0110

States: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 → back to 0

Step 2: State Table

We use JK Flip-Flops (Q3 = MSB, Q0 = LSB).

Step 3: JK Flip-Flop Excitation Table

Recall JK excitation:

Step 4: JK Input Table

States 1100 to 1111 never occur, so their entries are treated as don't-care conditions when the maps are simplified.

Simplified Flip-Flop Input Equations

Reading each column of the input table against the present state gives:

$$J_0 = K_0 = 1$$

$$J_1 = K_1 = Q_0$$

$$J_2 = \overline{Q_3} \cdot Q_1 \cdot Q_0 \qquad K_2 = Q_1 \cdot Q_0$$

$$J_3 = Q_2 \cdot Q_1 \cdot Q_0 \qquad K_3 = Q_1 \cdot Q_0$$

The least significant stage toggles on every pulse, so its inputs are tied to logic 1. Q1 toggles whenever Q0 is high. Q2 is set only at state 0011 and cleared only at state 0111, and the factor Q̄3 is essential: without it the counter would set Q2 while leaving state 1011 and would run to MOD-16. Q3 is set on leaving 0111 and cleared on leaving 1011, which is what folds the count back to zero after 11 and makes the modulus 12.

Logic Circuit

   +---+                                                     
   | 1 |----> J0, K0
   +---+
                Q0 -------------------> J1, K1

                Q1 ---+
                      +--[AND]--+------> K2  and  K3
                Q0 ---+         |
                                +--[AND with Q3']--> J2
                                |
                                +--[AND with Q2 ]--> J3

        +-------+   +-------+   +-------+   +-------+
   J0 ->|       |   |       |   |       |   |       |
        |  FF0  |   |  FF1  |   |  FF2  |   |  FF3  |
   K0 ->|       |   |       |   |       |   |       |
        +---+---+   +---+---+   +---+---+   +---+---+
            |           |           |           |
            Q0          Q1          Q2          Q3
            |           |           |           |
   CLK -----+-----------+-----------+-----------+
            (one common clock to all four flip-flops)

All four flip-flops share one clock line, and only two AND gates plus one inverter are needed to build the input logic, since the term Q₁·Q₀ is reused by K₂ and K₃.

Timing Sequence

Timing Diagram

Pulse     1    2    3    4    5    6    7    8    9   10   11   12
        __   __   __   __   __   __   __   __   __   __   __   __
CLK   _|  |_|  |_|  |_|  |_|  |_|  |_|  |_|  |_|  |_|  |_|  |_|  |_

Q0    ‾‾‾‾‾_____‾‾‾‾‾_____‾‾‾‾‾_____‾‾‾‾‾_____‾‾‾‾‾_____‾‾‾‾‾_____

Q1    _____‾‾‾‾‾‾‾‾‾‾__________‾‾‾‾‾‾‾‾‾‾__________‾‾‾‾‾‾‾‾‾‾_____

Q2    _______________‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾_______________________

Q3    _______________________________________‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾_____

Q₀ divides the clock by two, Q₁ by four and Q₂ by eight for as long as the count is below 8, while Q₃ stays high through counts 8 to 11 and falls on the twelfth pulse. The Q₃ waveform therefore has a period of twelve clock pulses, which confirms the modulus.

Conclusion

A parallel counter clocks all its flip-flops together, so its maximum speed is set by one flip-flop delay plus one gate delay rather than by the sum of the delays in the chain. The MOD-12 design above uses four JK flip-flops with $J_0 = K_0 = 1$, $J_1 = K_1 = Q_0$, $J_2 = \overline{Q_3}Q_1Q_0$, $K_2 = Q_1Q_0$, $J_3 = Q_2Q_1Q_0$ and $K_3 = Q_1Q_0$, which produces the repeating sequence 0 to 11 and returns to 0000 on the twelfth clock pulse.

Convert (257)₈ to Decimal and Hexadecimal

Given Data

• Number: $(257)_8$ (octal, base 8)
• Required: convert to hexadecimal (base 16) and decimal (base 10)

Part 1: Octal to Decimal

Multiply each digit by its positional weight (power of 8):

$$ (257)_8 = 2 \times 8^2 + 5 \times 8^1 + 7 \times 8^0 $$

$$ = 2 \times 64 + 5 \times 8 + 7 \times 1 $$

$$ = 128 + 40 + 7 = 175 $$

$$ \boxed{(257)8 = (175){10}} $$

Part 2: Octal to Hexadecimal (via Binary)

Step 1: Convert each octal digit to 3-bit binary

$$ (257)_8 = (010\ 101\ 111)_2 = (10101111)_2 $$

Step 2: Regroup binary into groups of 4 (from right)

$$ 10101111 \rightarrow 1010\ 1111 $$

(No padding needed here since 8 bits = two groups of 4.)

Step 3: Result

$$ \boxed{(257)8 = (AF){16}} $$

Verification (decimal check): $$ (AF){16} = 10 \times 16 + 15 = 160 + 15 = 175 = (175){10} \checkmark $$

Summary

Multiplexer: Definition and Implementation

Definition of Multiplexer

A multiplexer (MUX) is a combinational circuit that selects one of many input lines and forwards it to a single output line based on select lines. It is also called a data selector.

• An n-input multiplexer has:
  • 2^n data input lines
  • n select lines
  • 1 output line

Implementing 8×1 MUX Using 2×1 MUXes

Key Idea

• An 8×1 MUX has: 8 data inputs (I0-I7), 3 select lines (S2, S1, S0), and 1 output
• A 2×1 MUX has: 2 data inputs, 1 select line, 1 output

How Many 2×1 MUXes Are Needed?

To build an 8×1 MUX from 2×1 MUXes:

Total = 4 + 2 + 1 = 7 two-input MUXes

Circuit Description

Data Inputs        Stage 1 (S0)      Stage 2 (S1)     Stage 3 (S2)
-----------        ------------      ------------     ------------

I0 ─┐
    ├─ MUX1 ──┐
I1 ─┘  (S0)  │
              ├─ MUX5 ──┐
I2 ─┐         │  (S1)   │
    ├─ MUX2 ──┘         │
I3 ─┘  (S0)             ├─ MUX7 ──── Y (Output)
                         │   (S2)
I4 ─┐                   │
    ├─ MUX3 ──┐         │
I5 ─┘  (S0)  │         │
              ├─ MUX6 ──┘
I6 ─┐         │  (S1)
    ├─ MUX4 ──┘
I7 ─┘  (S0)

Operation (Truth Table of Selection)

Working Principle

1. Stage 1 (controlled by S0):

   • MUX1 selects between I0 and I1
   • MUX2 selects between I2 and I3
   • MUX3 selects between I4 and I5
   • MUX4 selects between I6 and I7

2. Stage 2 (controlled by S1):

   • MUX5 selects between outputs of MUX1 and MUX2
   • MUX6 selects between outputs of MUX3 and MUX4

3. Stage 3 (controlled by S2):

   • MUX7 selects between outputs of MUX5 and MUX6 to give the final output Y

Summary

An 8×1 MUX can be implemented using seven 2×1 MUXes arranged in three stages, where each stage is controlled by one select line (S0, S1, S2 respectively), progressively narrowing 8 inputs down to 1 output.

--- ASCII stands for American Standard Code for Information Interchange. - It is a 7-bit character encoding standard used to represent text in computers and communication devices. - A 7-bit ASCII code can represent 2⁷ = 128 different cha...

Design a combinational circuit with three inputs (A, B, C) where the output F = 1 when the binary value of the inputs is odd. --- Signal Description --------------------- A Most Significant Bit (MSB) B Middle Bit C Least Significant Bit ...

Parallel (Synchronous) Counter and MOD-12 Design

Definition of Parallel (Synchronous) Counter

A parallel counter (also called a synchronous counter) is a sequential digital circuit in which all flip-flops receive the clock pulse simultaneously. Unlike ripple (asynchronous) counters where each flip-flop triggers the next, in a synchronous counter the clock is applied in parallel to all flip-flops at the same time.

Key features:

• All flip-flops are clocked simultaneously
• No propagation delay accumulation (faster operation)
• Uses combinational logic (AND gates) to control flip-flop inputs
• Suitable for high-speed applications

MOD-12 Synchronous Up Counter Design

A MOD-12 counter counts from 0 to 11 (0000 to 1011 in binary) and then resets to 0. It requires 4 flip-flops (since 2^4 = 16 > 12).

Step 1: State Diagram

  0000 → 0001 → 0010 → 0011 → 0100 → 0101
    ↑                                      ↓
  1011 ← 1010 ← 1001 ← 1000 ← 0111 ← 0110

States: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 → back to 0

Step 2: State Table

We use JK Flip-Flops (Q3 = MSB, Q0 = LSB).

Step 3: JK Flip-Flop Excitation Table

Recall JK excitation:

Step 4: JK Input Table

States 1100 to 1111 never occur, so their entries are treated as don't-care conditions when the maps are simplified.

Simplified Flip-Flop Input Equations

Reading each column of the input table against the present state gives:

$$J_0 = K_0 = 1$$

$$J_1 = K_1 = Q_0$$

$$J_2 = \overline{Q_3} \cdot Q_1 \cdot Q_0 \qquad K_2 = Q_1 \cdot Q_0$$

$$J_3 = Q_2 \cdot Q_1 \cdot Q_0 \qquad K_3 = Q_1 \cdot Q_0$$

The least significant stage toggles on every pulse, so its inputs are tied to logic 1. Q1 toggles whenever Q0 is high. Q2 is set only at state 0011 and cleared only at state 0111, and the factor Q̄3 is essential: without it the counter would set Q2 while leaving state 1011 and would run to MOD-16. Q3 is set on leaving 0111 and cleared on leaving 1011, which is what folds the count back to zero after 11 and makes the modulus 12.

Logic Circuit

   +---+                                                     
   | 1 |----> J0, K0
   +---+
                Q0 -------------------> J1, K1

                Q1 ---+
                      +--[AND]--+------> K2  and  K3
                Q0 ---+         |
                                +--[AND with Q3']--> J2
                                |
                                +--[AND with Q2 ]--> J3

        +-------+   +-------+   +-------+   +-------+
   J0 ->|       |   |       |   |       |   |       |
        |  FF0  |   |  FF1  |   |  FF2  |   |  FF3  |
   K0 ->|       |   |       |   |       |   |       |
        +---+---+   +---+---+   +---+---+   +---+---+
            |           |           |           |
            Q0          Q1          Q2          Q3
            |           |           |           |
   CLK -----+-----------+-----------+-----------+
            (one common clock to all four flip-flops)

All four flip-flops share one clock line, and only two AND gates plus one inverter are needed to build the input logic, since the term Q₁·Q₀ is reused by K₂ and K₃.

Timing Sequence

Timing Diagram

Pulse     1    2    3    4    5    6    7    8    9   10   11   12
        __   __   __   __   __   __   __   __   __   __   __   __
CLK   _|  |_|  |_|  |_|  |_|  |_|  |_|  |_|  |_|  |_|  |_|  |_|  |_

Q0    ‾‾‾‾‾_____‾‾‾‾‾_____‾‾‾‾‾_____‾‾‾‾‾_____‾‾‾‾‾_____‾‾‾‾‾_____

Q1    _____‾‾‾‾‾‾‾‾‾‾__________‾‾‾‾‾‾‾‾‾‾__________‾‾‾‾‾‾‾‾‾‾_____

Q2    _______________‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾_______________________

Q3    _______________________________________‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾_____

Q₀ divides the clock by two, Q₁ by four and Q₂ by eight for as long as the count is below 8, while Q₃ stays high through counts 8 to 11 and falls on the twelfth pulse. The Q₃ waveform therefore has a period of twelve clock pulses, which confirms the modulus.

Conclusion

A parallel counter clocks all its flip-flops together, so its maximum speed is set by one flip-flop delay plus one gate delay rather than by the sum of the delays in the chain. The MOD-12 design above uses four JK flip-flops with $J_0 = K_0 = 1$, $J_1 = K_1 = Q_0$, $J_2 = \overline{Q_3}Q_1Q_0$, $K_2 = Q_1Q_0$, $J_3 = Q_2Q_1Q_0$ and $K_3 = Q_1Q_0$, which produces the repeating sequence 0 to 11 and returns to 0000 on the twelfth clock pulse.

Convert (257)₈ to Decimal and Hexadecimal

Given Data

• Number: $(257)_8$ (octal, base 8)
• Required: convert to hexadecimal (base 16) and decimal (base 10)

Part 1: Octal to Decimal

Multiply each digit by its positional weight (power of 8):

$$ (257)_8 = 2 \times 8^2 + 5 \times 8^1 + 7 \times 8^0 $$

$$ = 2 \times 64 + 5 \times 8 + 7 \times 1 $$

$$ = 128 + 40 + 7 = 175 $$

$$ \boxed{(257)8 = (175){10}} $$

Part 2: Octal to Hexadecimal (via Binary)

Step 1: Convert each octal digit to 3-bit binary

$$ (257)_8 = (010\ 101\ 111)_2 = (10101111)_2 $$

Step 2: Regroup binary into groups of 4 (from right)

$$ 10101111 \rightarrow 1010\ 1111 $$

(No padding needed here since 8 bits = two groups of 4.)

Step 3: Result

$$ \boxed{(257)8 = (AF){16}} $$

Verification (decimal check): $$ (AF){16} = 10 \times 16 + 15 = 160 + 15 = 175 = (175){10} \checkmark $$

Summary

Multiplexer: Definition and Implementation

Definition of Multiplexer

A multiplexer (MUX) is a combinational circuit that selects one of many input lines and forwards it to a single output line based on select lines. It is also called a data selector.

• An n-input multiplexer has:
  • 2^n data input lines
  • n select lines
  • 1 output line

Implementing 8×1 MUX Using 2×1 MUXes

Key Idea

• An 8×1 MUX has: 8 data inputs (I0-I7), 3 select lines (S2, S1, S0), and 1 output
• A 2×1 MUX has: 2 data inputs, 1 select line, 1 output

How Many 2×1 MUXes Are Needed?

To build an 8×1 MUX from 2×1 MUXes:

Total = 4 + 2 + 1 = 7 two-input MUXes

Circuit Description

Data Inputs        Stage 1 (S0)      Stage 2 (S1)     Stage 3 (S2)
-----------        ------------      ------------     ------------

I0 ─┐
    ├─ MUX1 ──┐
I1 ─┘  (S0)  │
              ├─ MUX5 ──┐
I2 ─┐         │  (S1)   │
    ├─ MUX2 ──┘         │
I3 ─┘  (S0)             ├─ MUX7 ──── Y (Output)
                         │   (S2)
I4 ─┐                   │
    ├─ MUX3 ──┐         │
I5 ─┘  (S0)  │         │
              ├─ MUX6 ──┘
I6 ─┐         │  (S1)
    ├─ MUX4 ──┘
I7 ─┘  (S0)

Operation (Truth Table of Selection)

Working Principle

1. Stage 1 (controlled by S0):

   • MUX1 selects between I0 and I1
   • MUX2 selects between I2 and I3
   • MUX3 selects between I4 and I5
   • MUX4 selects between I6 and I7

2. Stage 2 (controlled by S1):

   • MUX5 selects between outputs of MUX1 and MUX2
   • MUX6 selects between outputs of MUX3 and MUX4

3. Stage 3 (controlled by S2):

   • MUX7 selects between outputs of MUX5 and MUX6 to give the final output Y

Summary

An 8×1 MUX can be implemented using seven 2×1 MUXes arranged in three stages, where each stage is controlled by one select line (S0, S1, S2 respectively), progressively narrowing 8 inputs down to 1 output.

A − B Using 1's Complement Method

STEP 1 - EXTRACT (Given data)

• $A = 1010100$
• $B = 1000100$
• Operation: $A - B$ using 1's complement

Decimal check of inputs:

• $A = 1010100_2 = 64+16+4 = 84$
• $B = 1000100_2 = 64+4 = 68$

STEP 2 - SOLVE

Step 1: 1's Complement of B

Invert every bit of $B$:

B        = 1000100
1's comp = 0111011

Step 2: Add A and 1's complement of B

   1010100
 + 0111011
 ---------
  10001111

Bit-by-bit (right to left):

• $0+1 = 1$
• $0+1 = 1$
• $1+0 = 1$
• $0+1 = 1$
• $1+1 = 0$, carry 1
• $0+1+1 = 0$, carry 1
• $1+0+1 = 0$, carry 1 (carry out)

Result = $1,0001111$ (a carry out of 1 is generated).

Step 3: End-around carry

Since a carry is produced, the result is positive. Add the carry back to the 7-bit sum:

   0001111
 +       1
 ---------
   0010000

Step 4: Final Result

$$A - B = 0010000_2$$

Verification

$$0010000_2 = 16_{10}, \quad 84 - 68 = 16 \checkmark$$

Conclusion

$$A - B = 0010000_2 = 16_{10}$$

A decoder is a combinational logic circuit that converts binary coded input into a set of outputs, where exactly one output is active (HIGH) for each unique combination of inputs. - It has n input lines and 2^n output lines - It "decodes...

--- ASCII stands for American Standard Code for Information Interchange. - It is a 7-bit character encoding standard used to represent text in computers and communication devices. - A 7-bit ASCII code can represent 2⁷ = 128 different cha...

In an SR (Set-Reset) flip-flop, the inputs S and R must not be applied simultaneously as logic 1. When S = 1 and R = 1 at the same time, the output becomes indeterminate (unpredictable): both Q and Q' try to become 1 simultaneously, whic...

A half-subtractor is a combinational logic circuit that performs subtraction of two single-bit binary numbers. It produces two outputs: the Difference (D) and the Borrow (B). - It subtracts the subtrahend (B) from the minuend (A) - It do...

A JK flip flop is an improved version of the SR flip flop that eliminates the invalid/indeterminate state. It has two inputs: J (Set) and K (Reset), along with a Clock input and outputs Q and Q'. --- Internal Gate Implementation: --- CLK...

Boolean Function F = AB + B'C: Sum of Maxterms

Step 1 - Given Data

• Boolean function: $F = AB + B'C$
• Variables: $A, B, C$ (3 variables, so $2^3 = 8$ combinations)
• Required: express as product (sum) of maxterms, with truth table; list two uses.

Step 2 - Solve

Truth Table

Check of B'C: when B=0, B'=1, so B'C = C. Rows 1 (C=1) and 5 (C=1) give 1. Rows where AB=1 are 6 and 7. All consistent.

Identifying Maxterms

Maxterms correspond to rows where F = 0: rows 0, 2, 3, 4.

Rule: variable appears uncomplemented if its bit = 0, complemented if its bit = 1.

Product of Maxterms Form

$$F = \prod M(0, 2, 3, 4)$$

$$\boxed{F = (A+B+C)(A+B'+C)(A+B'+C')(A'+B+C)}$$

Verification

Minterms (F = 1) at rows 1, 5, 6, 7: $$F = \sum m(1,5,6,7)$$ The two sets ${0,2,3,4}$ and ${1,5,6,7}$ are complementary and together cover all 8 rows. Correct.

Two Uses of Sum (Product) of Maxterms

1. OR-AND (two-level) circuit implementation: The POS canonical form maps directly to an OR-AND gate structure, which is economical when there are fewer 0-outputs than 1-outputs.

2. Canonical/standard reference form: It provides a unique standardized representation of a function, useful as a starting point for minimization (K-map, Quine-McCluskey) and for comparing whether two Boolean expressions are equivalent.

• (a) Convert $(0.625){10}$ to binary - (b) Convert $(173)8$ to decimal --- Method: Multiply the fractional part by 2 repeatedly, recording the integer part each time, reading top to bottom. Step Fraction × 2 Result Bit -----------------...

Function (SOP): $$F = B'C'D' + BCD' + ABCD'$$ Don't-care conditions: $$d = B'CD' + A'BC'D$$ Variables: A, B, C, D (4 variables → minterms 0 to 15) --- Order of bits: A B C D. - $B'C'D'$ → B=0, C=0, D=0, A free → A=0: 0000 = m₀, A=1: 1000...

Magnitude Comparator

Definition (2 marks)

A magnitude comparator is a combinational logic circuit that compares two binary numbers and determines their relative magnitudes. Given two n-bit numbers A and B, the comparator produces three output signals:

• A > B (output is HIGH when A is greater than B)
• A = B (output is HIGH when A equals B)
• A < B (output is HIGH when A is less than B)

Design of 4-bit Magnitude Comparator (8 marks)

Given

Two 4-bit numbers:

• A = A₃A₂A₁A₀
• B = B₃B₂B₁B₀

Step 1: Basic Bit Comparison

For each bit position i, define:

So define equality bits:

x₃ = A₃B₃ + Ā₃B̄₃
x₂ = A₂B₂ + Ā₂B̄₂
x₁ = A₁B₁ + Ā₁B̄₁
x₀ = A₀B₀ + Ā₀B̄₀

Step 2: Derive Output Expressions

Equality Output: (A = B)

All bit pairs must be equal:

(A = B) = x₃ · x₂ · x₁ · x₀

Greater Than Output: (A > B)

A > B if the most significant differing bit of A is 1 and B is 0:

(A > B) = A₃B̄₃
         + x₃·A₂B̄₂
         + x₃·x₂·A₁B̄₁
         + x₃·x₂·x₁·A₀B̄₀

Less Than Output: (A < B)

A < B if the most significant differing bit of B is 1 and A is 0:

(A < B) = Ā₃B₃
         + x₃·Ā₂B₂
         + x₃·x₂·Ā₁B₁
         + x₃·x₂·x₁·Ā₀B₀

Note: Alternatively, (A < B) = NOT(A > B) + NOT(A = B), i.e., (A < B) = (A > B)' · (A = B)'

Step 3: Logic Circuit Block Diagram

A₃,B₃ ──► [XNOR]──► x₃ ──────────────────────────────────────────►|
A₂,B₂ ──► [XNOR]──► x₂ ──────────────────────────────────────────►| AND ──► (A=B)
A₁,B₁ ──► [XNOR]──► x₁ ──────────────────────────────────────────►|
A₀,B₀ ──► [XNOR]──► x₀ ──────────────────────────────────────────►|

For (A > B):
A₃B̄₃ ──────────────────────────────────────────────────────────────►|
x₃·A₂B̄₂ ───────────────────────────────────────────────────────────►| OR ──► (A>B)
x₃·x₂·A₁B̄₁ ────────────────────────────────────────────────────────►|
x₃·x₂·x₁·A₀B̄₀ ─────────────────────────────────────────────────────►|

For (A < B):
Ā₃B₃ ──────────────────────────────────────────────────────────────►|
x₃·Ā₂B₂ ───────────────────────────────────────────────────────────►| OR ──► (A<B)
x₃·x₂·Ā₁B₁ ────────────────────────────────────────────────────────►|
x₃·x₂·x₁·Ā₀B₀ ─────────────────────────────────────────────────────►|

Step 4: Verification Example

Let A = 1010 (10) and B = 0110 (6):

• (A = B) = x₃·x₂·x₁·x₀ = 0·0·1·1 = 0 ✓
• (A > B) = A₃B̄₃ = 1·1 = 1 ✓ (since MSB of A is 1, MSB of B is 0)
• (A < B) = Ā₃B₃ = 0·0 = 0 ✓

A Master-Slave J-K flip-flop is a cascaded combination of two clocked SR flip-flops (or J-K stages) connected in series, designed to eliminate the race-around condition (indeterminate state) that occurs in a simple clocked J-K flip-flop ...