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Computer Architecture 2077 question paper

The complete TU 2077 exam paper for Computer Architecture (CSC213), all 12 questions with solved model answers written to the mark scheme.

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110 marksNumericalPipeliningHideAnswer
What do you mean by pipeline? Explain with space time diagram for a six segmented pipeline showing the time it takes to process eight tasks.[10]
Pipeline: Definition and Space-Time Diagram

STEP 1 - Given Data
- Number of pipeline segments: $k = 6$
- Number of tasks to be processed: $n = 8$
(All required numeric values are present.)

STEP 2 - Solution

What is a Pipeline?

A pipeline is a technique of decomposing a sequential process into sub-operations, with each sub-operation being executed in a dedicated segment that operates concurrently with all other segments. Information flows through the segments much like an industrial assembly line: while one segment works on one task, another segment simultaneously works on a different task.

Each segment consists of a combinational circuit that performs a sub-operation, followed by a register (latch) that holds the intermediate result to be passed to the next segment on the next clock pulse. All registers are controlled by a common clock.

The diagram that shows which segment is busy with which task at each clock period is called a space-time diagram.

Total Time for a k-Segment Pipeline Processing n Tasks

For a $k$ -segment pipeline executing $n$ tasks, the number of clock cycles required is:

$\text{Total Clock Cycles} = k + (n - 1)$

Substituting $k = 6$ and $n = 8$ :

$= 6 + (8 - 1) = 6 + 7 = \boxed{13 \text{ clock cycles}}$
- The first task fills all 6 segments and completes at the end of clock cycle 6.
- Thereafter, one task completes at every clock cycle, so the remaining 7 tasks finish in the next 7 cycles (cycles 7 to 13).
Space-Time Diagram (6 segments, 8 tasks)
Segment | Clock Cycles | 1 2 3 4 5 6 7 8 9 10 11 12 13 --------|------------------------------------------------------ S1 | T1 T2 T3 T4 T5 T6 T7 T8 . . . . . S2 | . T1 T2 T3 T4 T5 T6 T7 T8 . . . . S3 | . . T1 T2 T3 T4 T5 T6 T7 T8 . . . S4 | . . . T1 T2 T3 T4 T5 T6 T7 T8 . . S5 | . . . . T1 T2 T3 T4 T5 T6 T7 T8 . S6 | . . . . . T1 T2 T3 T4 T5 T6 T7 T8
Each task moves diagonally through the six segments.

Task Completes at cycle
T1 6
T2 7
T3 8
T4 9
T5 10
T6 11
T7 12
T8 13

Speedup Compared with Non-Pipelined Execution

Method Time Required
Non-pipelined $n \times k = 8 \times 6 = 48$ cycles
Pipelined $k + (n-1) = 13$ cycles

Speedup:

$S = \frac{n \times k}{k + (n-1)} = \frac{48}{13} \approx 3.69$

As $n \to \infty$ , the maximum speedup approaches $k = 6$ .

Conclusion

A pipeline overlaps the execution of tasks across multiple segments. A six-segment pipeline processing eight tasks needs only 13 clock cycles (against 48 without pipelining), giving a speedup of about 3.69. The space-time diagram confirms that once the pipeline is full (from cycle 6), one task completes every clock cycle.
Pipeline: Definition and Space-Time Diagram

STEP 1 - Given Data
- Number of pipeline segments: $k = 6$
- Number of tasks to be processed: $n = 8$
(All required numeric values are present.)

STEP 2 - Solution

What is a Pipeline?

A pipeline is a technique of decomposing a sequential process into sub-operations, with each sub-operation being executed in a dedicated segment that operates concurrently with all other segments. Information flows through the segments much like an industrial assembly line: while one segment works on one task, another segment simultaneously works on a different task.

Each segment consists of a combinational circuit that performs a sub-operation, followed by a register (latch) that holds the intermediate result to be passed to the next segment on the next clock pulse. All registers are controlled by a common clock.

The diagram that shows which segment is busy with which task at each clock period is called a space-time diagram.

Total Time for a k-Segment Pipeline Processing n Tasks

For a $k$-segment pipeline executing $n$ tasks, the number of clock cycles required is:

$$\text{Total Clock Cycles} = k + (n - 1)$$

Substituting $k = 6$ and $n = 8$:

$$= 6 + (8 - 1) = 6 + 7 = \boxed{13 \text{ clock cycles}}$$
- The first task fills all 6 segments and completes at the end of clock cycle 6.
- Thereafter, one task completes at every clock cycle, so the remaining 7 tasks finish in the next 7 cycles (cycles 7 to 13).
Space-Time Diagram (6 segments, 8 tasks)
Segment | Clock Cycles | 1 2 3 4 5 6 7 8 9 10 11 12 13 --------|------------------------------------------------------ S1 | T1 T2 T3 T4 T5 T6 T7 T8 . . . . . S2 | . T1 T2 T3 T4 T5 T6 T7 T8 . . . . S3 | . . T1 T2 T3 T4 T5 T6 T7 T8 . . . S4 | . . . T1 T2 T3 T4 T5 T6 T7 T8 . . S5 | . . . . T1 T2 T3 T4 T5 T6 T7 T8 . S6 | . . . . . T1 T2 T3 T4 T5 T6 T7 T8
Each task moves diagonally through the six segments.

Task Completes at cycle
T1 6
T2 7
T3 8
T4 9
T5 10
T6 11
T7 12
T8 13

Speedup Compared with Non-Pipelined Execution

Method Time Required
Non-pipelined $n \times k = 8 \times 6 = 48$ cycles
Pipelined $k + (n-1) = 13$ cycles

Speedup:

$$S = \frac{n \times k}{k + (n-1)} = \frac{48}{13} \approx 3.69$$

As $n \to \infty$, the maximum speedup approaches $k = 6$.

Conclusion

A pipeline overlaps the execution of tasks across multiple segments. A six-segment pipeline processing eight tasks needs only 13 clock cycles (against 48 without pipelining), giving a speedup of about 3.69. The space-time diagram confirms that once the pipeline is full (from cycle 6), one task completes every clock cycle.
210 marksNumericalBooth MultiplicationHideAnswer
Explain Booth multiplication algorithm with hardware implementation diagram. Multiply (-4) x (-3) using Booth multiplication algorithm.[10]
Booth's algorithm is a technique for multiplying two signed binary numbers represented in 2's complement form. It treats both positive and negative multipliers uniformly and reduces the number of arithmetic operations by examining pairs ...
310 marksModes of TransferHideAnswer
Define I/O interface. Comparison between programmed I/O, Interrupt driven I/O and direct memory access (DMA).[10]
--- An Input/Output (I/O) Interface provides a method for transferring information between internal storage (CPU/Memory) and external I/O devices (peripherals). It is needed because several differences exist between the computer and peri...
45 marksProgram Interrupt & Interrupt CycleHideAnswer
Draw an instruction cycle state diagram with interrupt and explain it. [5]
--- When the computer starts, the following registers are initialized: - SC (Sequence Counter) is cleared to 0 - IEN (Interrupt Enable flip-flop) is cleared to 0 - R (Interrupt Request flip-flop) is cleared to 0 --- The instruction cycle...
55 marksRegister Transfer LanguageHideAnswer
Explain register transfer language with example. [5]
Register Transfer Language (RTL) is a symbolic notation used to describe the micro-operations and data transfers that occur among registers in a digital computer. It provides a concise and formal way to express how data moves between reg...
65 marksNumericalInstruction FormatsHideAnswer
Write codes using 3, 2 and 1 address instruction formats to perform the given operations. $X = A/B + C * D/C$ [5]
Write codes using 3, 2 and 1 address instruction formats to perform the given operations. $X = A/B + C * D/C$ [5]
Expression to evaluate: $X = A/B + C \ast D / C$ - Required formats: 3-address, 2-address, 1-address instructions. $X = (A/B) + ((C \ast D)/C)$ Sub-operations: 1. $T1 = A/B$ 2. $T2 = C \ast D$ 3. $T3 = T2/C$ 4. $X = T1 + T3$ --- Form...

Expression to evaluate: $X = A/B + C \ast D / C$ - Required formats: 3-address, 2-address, 1-address instructions. $$X = (A/B) + ((C \ast D)/C)$$ Sub-operations: 1. $T1 = A/B$ 2. $T2 = C \ast D$ 3. $T3 = T2/C$ 4. $X = T1 + T3$ --- Form...
75 marksAddressing ModesHideAnswer
Explain the various addressing modes with example. [5]
An addressing mode specifies how the operand (or the address of the operand) is determined from the instruction. Different addressing modes provide flexibility in accessing data stored in registers, memory, or within the instruction itse...
85 marksDesign of Control UnitHideAnswer
Differentiate between hardwired control unit and microprogrammed control unit. [5]
Hardwired Control Unit: A control unit in which control signals are generated by hardware using conventional logic design techniques. It generates a specific sequence of control signals directly through logic circuits. Microprogrammed Co...
95 marksPipeliningHideAnswer
How performance of computer is increased using pipeline? Explain with practical example. [5]
A pipeline is a technique where multiple instruction phases are overlapped in execution to improve the throughput of a computer. Instead of completing one instruction fully before starting the next, different stages of different instruct...
105 marksDivision of Signed magnitude DataHideAnswer
Differentiate between restoring division and non-restoring division. [5]
Both are hardware algorithms used to divide unsigned integers using shift and subtract operations, but they differ in how they handle the case when the partial remainder becomes negative. --- Feature Restoring Division Non-Restoring Divi...
115 marksCache MemoryHideAnswer
Give the appropriate reasons why replacement algorithm is required in associative mapping? [5]
In associative mapping, any block from main memory can be loaded into any line (slot) of the cache. This is the most flexible cache organization because there is no restriction on placement. However, this very flexibility creates a criti...
125 marksInput-Output InterfaceHideAnswer
Differentiate between isolated versus memory mapped I/O. [5]
Isolated I/O and Memory-Mapped I/O are two different techniques used by a CPU to communicate with I/O devices. They differ primarily in how address spaces and instructions are organized. --- Feature Isolated I/O Memory-Mapped I/O -------...

Task	Completes at cycle
T1	6
T2	7
T3	8
T4	9
T5	10
T6	11
T7	12
T8	13

Method	Time Required
Non-pipelined	$n \times k = 8 \times 6 = 48$ cycles
Pipelined	$k + (n-1) = 13$ cycles

Task	Completes at cycle
T1	6
T2	7
T3	8
T4	9
T5	10
T6	11
T7	12
T8	13

Method	Time Required
Non-pipelined	$n \times k = 8 \times 6 = 48$ cycles
Pipelined	$k + (n-1) = 13$ cycles

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Computer Architecture 2077 question paper

Pipeline: Definition and Space-Time Diagram

STEP 1 - Given Data

STEP 2 - Solution

What is a Pipeline?

Total Time for a k-Segment Pipeline Processing n Tasks

Space-Time Diagram (6 segments, 8 tasks)

Speedup Compared with Non-Pipelined Execution

Conclusion

Pipeline: Definition and Space-Time Diagram

STEP 1 - Given Data

STEP 2 - Solution

What is a Pipeline?

Total Time for a k-Segment Pipeline Processing n Tasks

Space-Time Diagram (6 segments, 8 tasks)

Speedup Compared with Non-Pipelined Execution

Conclusion

Pipeline: Definition and Space-Time Diagram

STEP 1 - Given Data

STEP 2 - Solution

What is a Pipeline?

Total Time for a k-Segment Pipeline Processing n Tasks

Space-Time Diagram (6 segments, 8 tasks)

Speedup Compared with Non-Pipelined Execution

Conclusion