Computer Organization and Architecture 2025-26 question paper

A bus is a group of common wires used to carry information between the units of a computer. Different types are used.

• Address bus: carries the memory or I/O address from the CPU. It is one way.
• Data bus: carries the data between the CPU, memory and I/O. It is two way.
• Control bus: carries signals such as read, write, clock and interrupt, to control the other buses.

Together, they form the system bus.

A digital computer has five functional units. The input unit accepts data and programs. The memory unit stores them. The arithmetic and logic unit (ALU) does addition, subtraction and logic operations. The control unit fetches and decodes instructions and sends control signals to all other units. The output unit shows the results. The ALU and the control unit together form the CPU. The units are joined by a system bus.

Bus architecture is the way a common set of wires is arranged to connect the CPU, memory and I/O devices. It has three parts: an address bus, a data bus and a control bus. A single shared bus is cheap and simple, but only one transfer can occur at a time. Large systems use many buses, such as a fast local bus and a slower I/O bus, joined by a bridge.

Its role is to let any unit communicate with any other over the same wires. It cuts the number of connections, makes it easy to add devices, and uses standard signals. An arbiter decides who uses it.

A register is a small, very fast storage place inside the CPU that holds a word of data, an address or an instruction. It is made of flip-flops.

General-purpose registers (such as R0 to R15) can be used by the programmer for any purpose, such as holding operands, results or addresses.

Special-purpose registers have a fixed job. Examples are the program counter (address of the next instruction), instruction register (the present instruction), stack pointer (top of stack), memory address register, memory data register, accumulator and the status (flag) register.

A carry look-ahead adder finds all carries at once. It uses $G_i = A_iB_i$ and $P_i = A_i \oplus B_i$, with $C_{i+1} = G_i + P_iC_i$ and $S_i = P_i \oplus C_i$.

Example: add $A = 1011$ and $B = 0110$ with $C_0 = 0$. Here $G = 0010$ and $P = 1101$ (bit 3 to bit 0). The look-ahead equations give $C_1 = 0$, $C_2 = G_1 = 1$, $C_3 = G_2 + P_2G_1 = 1$ and $C_4 = 1$. The sums $P_i \oplus C_i$ are $S_3S_2S_1S_0 = 0001$, so the result is $10001 = 17$, which equals $11 + 6$.

Booth's algorithm multiplies signed 2's complement numbers. For each bit pair $Q_0Q_{-1}$: $10$ subtracts $M$, $01$ adds $M$, otherwise nothing. Then it shifts right (ASR).

Here $M = -5 = 1011$, $-M = 0101$ and $Q = 3 = 0011$.

$AQ = 11110001 = -15$. Therefore $(-5) \times 3 = -15$.

A floating point number stores a real number as a sign, an exponent and a fraction, in the form $(-1)^s \times 1.f \times 2^{e}$.

Its components are:

• Sign bit: 0 for positive and 1 for negative.
• Exponent: the power of 2, stored with a bias so it is always positive. IEEE 754 single precision has 8 exponent bits and bias 127.
• Fraction (mantissa): the digits after the implied leading 1. Single precision has 23 fraction bits.

The exponent sets the range and the fraction sets the accuracy.

An array multiplier makes all the partial products at the same time with AND gates, and adds them with a regular array of adders. Here $A = 1101$ ($13$) is the multiplicand and $B = 1011$ ($11$) is the multiplier.

Each bit of $B$ is ANDed with every bit of $A$. If the multiplier bit is 1, the row is a copy of $A$. If it is 0, the row is all zeros. Each row is shifted one place left from the one above it:

Now the rows are added column by column. In hardware, this is done by full adders and half adders arranged in a grid. The carry of each adder goes to the next column, and the sum goes to the adder in the row below.

$$00001101 + 00011010 = 00100111$$

$$00100111 + 00000000 = 00100111$$

$$00100111 + 01101000 = 10001111$$

Therefore $1101 \times 1011 = 10001111_2$, which is $128 + 8 + 4 + 2 + 1 = 143$. Check: $13 \times 11 = 143$.

Structure. For an $n \times n$ multiplier, the array needs $n^2$ AND gates and about $n(n-1)$ adders. For 4 bits this means 16 AND gates and 12 adders (a mix of full adders and half adders). All partial products are formed in one gate delay. The total delay is the time for a carry and a sum to pass through the array, which grows in proportion to $n$.

Advantages. The design is regular and easy to lay out on a chip. It needs no clock or control unit, since it is purely combinational. It is much faster than the shift-and-add method, which needs $n$ clock cycles.

Disadvantage. The hardware grows as $n^2$, so large multipliers need a lot of area.

The ALU is a combinational circuit that performs arithmetic and logic micro-operations on two $n$-bit inputs. The design is made one bit at a time. Each bit has a 1-bit slice, and $n$ slices are joined side by side. The carry of one slice goes to the next.

        A_i        B_i
         |          |
         |   +------+------+
         |   | logic for B  |<-- S1 S0 (select B, B', 0, 1)
         |   +------+------+
         |          |
      +--+----------+--+
      |   full adder    |<-- C_i
      +--+--------------+--> C_i+1
         |
      +--+------------------+
      | logic gates AND,OR, |<-- S3 S2 (select)
      | XOR, NOT on A_i,B_i |
      +--+------------------+
         |
      [4:1 MUX] --> F_i

The arithmetic part is a parallel adder. A set of gates on the $B$ input decides what the adder sees. They can pass $B$, pass $\overline{B}$, or pass all 0s or all 1s. With the carry input $C_0$, this gives the different operations.

The logic part applies a gate to each bit pair separately. It gives AND, OR, XOR and complement (NOT). No carry moves between the bits.

A multiplexer (MUX) in each slice chooses between the arithmetic result and the logic result, using the select lines. The ALU also gives status flags: carry $C$, sign $S$, zero $Z$ and overflow $V$. Overflow is $V = C_n \oplus C_{n-1}$, the XOR of the last two carries.

Operations performed

• Arithmetic: addition, subtraction, increment, decrement and transfer.
• Logical: AND, OR, XOR, NOT.
• Shift: logical shift and arithmetic shift left or right, and rotate.

The control unit gives the select code that picks the operation. The result goes to a register, and the flags are stored in the status register for conditional branches.

Floating point numbers are stored as sign, exponent and mantissa, so their arithmetic needs extra steps on the exponents.

Addition and subtraction. (1) Compare the exponents. (2) Shift the mantissa of the smaller number right, and raise its exponent by 1 for every shift, until the exponents are equal. (3) Add or subtract the mantissas. (4) Normalise the result so it is again in the form $1.f$, and adjust the exponent. (5) Round the result and check for overflow or underflow.

Multiplication. Add the exponents, subtract the bias, multiply the mantissas, and normalise. The sign is the XOR of the signs.

Division. Subtract the exponents, add the bias, divide the mantissas, and normalise.

Example: $5.75 + (-2.5)$ in IEEE 754 single precision

In binary, $5.75 = 101.11_2 = 1.0111_2 \times 2^{2}$ and $2.5 = 10.1_2 = 1.01_2 \times 2^{1}$. The stored exponents are $2 + 127 = 129 = 10000001$ and $1 + 127 = 128 = 10000000$. So:

The exponents differ by 1, so shift the mantissa of $-2.5$ one place right. It becomes $-0.101_2 \times 2^{2}$.

The signs differ, so this is a subtraction of the mantissas:

$$1.0111 - 0.1010 = 0.1101$$

The result is $0.1101_2 \times 2^{2}$. It is not normalised, so shift left by one place and reduce the exponent by 1:

$$0.1101_2 \times 2^{2} = 1.101_2 \times 2^{1}$$

The sign is $0$, the stored exponent is $1 + 127 = 128 = 10000000$, and the fraction is $10100000000000000000000$.

In hexadecimal this is $\text{0x40500000}$. The value is $1.101_2 \times 2 = 11.01_2 = 3.25$. Therefore $5.75 + (-2.5) = 3.25$, which is correct.

Types of instructions

An instruction tells the CPU one operation. By their job, instructions fall into these groups.

• Data transfer: move data between registers and memory, for example LOAD, STORE, MOV, PUSH, POP.
• Arithmetic: ADD, SUB, MUL, DIV, INC, DEC.
• Logical and shift: AND, OR, XOR, NOT, shifts and rotates.
• Program control: JMP, conditional branches such as JZ, CALL and RET. They change the value of PC.
• Input and output: IN and OUT, which move data to and from devices.

Instruction formats

An instruction word has an opcode, which tells the operation, and operand fields, which tell where the data is. It may also have a mode field for the addressing mode. The number of address fields decides the format.

Take the statement $X = (A + B) \times (C + D)$ to see each format.

Three-address format. Each instruction has two sources and one destination.

ADD R1, A, B      ; R1 = A + B
ADD R2, C, D      ; R2 = C + D
MUL X, R1, R2     ; X = R1 * R2

The program is short, but the instructions are long.

Two-address format. The first operand is also the destination.

MOV R1, A
ADD R1, B
MOV R2, C
ADD R2, D
MUL R1, R2
MOV X, R1

This is the common format in x86 processors.

One-address format. The accumulator AC is the second operand and the destination.

LOAD A
ADD B
STORE T
LOAD C
ADD D
MUL T
STORE X

Zero-address format. Operands are taken from the top of a stack, so the instruction names no address. Only PUSH and POP name a memory address.

PUSH A
PUSH B
ADD
PUSH C
PUSH D
ADD
MUL
POP X

The programs use 3, 6, 7 and 8 instructions. More address fields mean fewer instructions, but longer ones. A zero-address instruction is the shortest, but it needs more of them.

Choosing a format. The three-address format is used in RISC machines such as MIPS, where registers hold the operands, so the fields are short. The two-address format is common in CISC machines such as x86. The one-address format was used in early machines with a single accumulator. The zero-address format is used in stack machines, for example in the evaluation of expressions and in the Java virtual machine. The choice is a balance between program length, instruction length and speed.

Instruction length. For example, if the opcode is 8 bits and each register field is 5 bits, a three-register instruction needs $8 + 3 \times 5 = 23$ bits, and it fits in a 32 bit word with room for a mode field.

RISC architecture

RISC means Reduced Instruction Set Computer. Its idea is that most programs use a few simple instructions most of the time. So the processor is built to run these very fast, and complex jobs are made from many simple instructions.

Features

• A small set of simple instructions, of fixed length, such as 32 bits.
• Each instruction takes one clock cycle, in most cases.
• Only LOAD and STORE instructions access memory. All other instructions work on registers. This is the load-store architecture.
• A large set of registers, often with overlapping register windows, which makes the procedure calls fast.
• Few and simple addressing modes.
• A hardwired control unit, with no microcode.
• A pipeline that is easy to build and keep full, as all the instructions are alike.

Advantages

• Higher speed, because of one-cycle instructions and good pipelining.
• A simple control unit, so a smaller chip, lower design time and lower cost.
• Less power use, which is the reason ARM is used in phones.
• Easier for compilers to optimize, as the instructions are regular.

Disadvantages. The programs are longer, as more instructions are needed, and they need more memory for code.

Comparison of RISC and CISC

In short, RISC moves the complexity from the hardware to the software, and CISC does the reverse.

Instruction pipelining

Instruction pipelining splits the execution of an instruction into stages, such as fetch, decode, execute, memory access and write back. Each stage has its own hardware. While one instruction is in a later stage, the next instruction is already in an earlier stage. So many instructions are in progress at the same time, and one instruction can finish in every clock cycle once the pipeline is full.

For $k$ stages, $n$ instructions and a stage time $t_p$, the times are:

$$T_{non\text{-}pipelined} = n,k,t_p$$

$$T_{pipelined} = (k + n - 1),t_p$$

$$\text{Speedup} = \frac{T_{non\text{-}pipelined}}{T_{pipelined}}$$

Numerical

Here the number of stages is $k = 5$, the stage time is $t_p = 20$ ns, and the number of instructions is $n = 10$.

(i) Without pipelining. Each instruction passes through all 5 stages one after the other, and the next one starts only after it ends. So one instruction takes $5 \times 20 = 100$ ns.

$$T_{non\text{-}pipelined} = 10 \times 5 \times 20 = 1000 \text{ ns}$$

(ii) With pipelining. The first instruction needs 5 cycles to come out. After that, each of the remaining 9 instructions finishes in one more cycle. So the total is $5 + 9 = 14$ cycles.

$$T_{pipelined} = (5 + 10 - 1) \times 20 = 14 \times 20 = 280 \text{ ns}$$

(iii) Speedup.

$$\text{Speedup} = \frac{1000}{280} \approx 3.57$$

Therefore the pipeline needs 280 ns for 10 instructions instead of 1000 ns, and the speedup is about 3.57. It is less than the ideal value 5, because the pipeline takes time to fill. If more instructions are run, the speedup comes closer to 5. For 1000 instructions, it would be $5000/1004 \approx 4.98$.

Remark. The result shows why pipelining is used. The total time falls from 1000 ns to 280 ns, though one instruction still takes 100 ns from start to end. The gain is in the throughput, which is the number of instructions finished per unit time. Hazards such as data dependencies would add stall cycles and lower the speedup further.

Hardwired control unit

A hardwired control unit makes the control signals with a fixed network of logic gates, decoders and flip-flops. There is no control memory. The signals depend on the opcode, the timing pulse and the status flags.

Design

 IR (opcode) -> [Instruction decoder] -> D0 ... D7 --+
                                                     v
 Clock -> [Sequence counter] -> [Timing decoder] --> [Control logic] -> control signals
              ^   T0 ... T15                          ^   (AND, OR gates)
              |                                       |
         clear (end of instruction)           Flags, mode bit I, interrupt R

The parts are:

• Instruction register and decoder. The opcode bits go to a decoder, for example 3 to 8. It makes one line $D_0$ to $D_7$ high for the current instruction.
• Sequence counter and timing decoder. The counter counts clock pulses. A 4 to 16 decoder makes the timing signals $T_0$ to $T_{15}$. Each signal gives one time slot for a micro operation.
• Control logic network. AND and OR gates combine the decoder lines, the timing signals and the flags. There is a Boolean equation for each control signal. For example, the signal to load AR is

$$AR\text{ load} = R'T_0 + R'T_2,D_7,I'$$

• Flags and condition bits. The zero flag, the carry flag and the mode bit I affect some of the signals.

Working

At $T_0$, $T_1$ and $T_2$ the same fetch signals appear for every instruction. After decoding, the line $D_i$ of the instruction and the later timing signals $T_3$, $T_4$, ... create the signals for the execute part. At the end, a signal clears the sequence counter, and the next instruction is fetched.

Advantages

• Very fast, since the signals come straight from gates.
• Good for RISC and pipelined designs.
• No control memory is needed.

Disadvantages

• The design is complex for a large instruction set, as every signal needs its own equation.
• It is hard to change. A new instruction means a new circuit.
• Error fixing is difficult and costly.
• Less regular, and it takes a long design time.

Use. Hardwired control is chosen in RISC processors, where the instructions are few and simple, so the equations are small and the speed matters more than flexibility.

A micro operation is a basic operation on the data stored in registers, done in one clock pulse. A machine instruction is carried out as a sequence of micro operations. They fall into four types.

1. Register transfer micro operations. They copy data from one register to another. For example, $R2 \leftarrow R1$ copies R1 into R2, and $AR \leftarrow PC$ moves the program counter to the address register. Memory transfers are written as $DR \leftarrow M[AR]$ (read) and $M[AR] \leftarrow DR$ (write). A transfer may happen only under a condition, such as $P: R2 \leftarrow R1$.

2. Arithmetic micro operations. They do arithmetic on the numbers in registers.

3. Logic micro operations. They work on each bit of the registers separately. Examples are AND, OR, XOR and NOT. For instance, $R1 \leftarrow R1 \wedge R2$ is used to clear selected bits (masking). XOR can be used to find the bits that differ, and OR can set bits.

4. Shift micro operations. They move the bits of a register to the left or right. A logical shift puts in a zero. A circular shift (rotate) puts the bit that goes out back at the other end. An arithmetic shift keeps the sign bit. A left arithmetic shift multiplies by 2, and a right arithmetic shift divides by 2. For example, shifting 0110 (6) to the left by one gives 1100, and logical right shift of 0110 gives 0011 (3).

Use in the control unit. The control unit makes the control signals that run the micro operations in the right order. For example, the fetch cycle is the sequence of micro operations $AR \leftarrow PC$, then $IR \leftarrow M[AR]$ and $PC \leftarrow PC + 1$. In a microprogrammed unit, each microinstruction names one or more micro operations. So all work of a computer finally reduces to these four types.

Memory hierarchy

A computer uses several kinds of memory, arranged in levels. The levels near the CPU are small, fast and costly. The levels far from the CPU are large, slow and cheap.

The levels are CPU registers, cache, main memory, magnetic disk, and tape or optical disk. Going down the hierarchy, the size and access time grow and the cost per bit falls. The hierarchy works because of locality of reference: programs reuse recent data and use data near it. So most accesses are served by the fast upper levels, and the system looks like a memory that is as fast as the cache and as large as the disk. Data moves between the cache and main memory in blocks, and between main memory and disk in pages.

Numerical

The chip has a capacity of $64\text{K} \times 8$. That is 65536 words of 8 bits each.

(i) The number of address lines is

$$\log_2 65536 = 16$$

So 16 address lines are needed.

(ii) The required memory is $256\text{K} \times 16$. The number of chips is

$$\frac{256\text{K} \times 16}{64\text{K} \times 8} = 4 \times 2 = 8$$

So 8 chips are needed.

The word width is 16 bits and a chip gives only 8 bits, so 2 chips are put side by side to make a 16-bit word. The memory has 256K words and a chip has 64K words, so 4 such rows of chips are needed to get 256K words. The chips form 4 rows and 2 columns.

The system has $256\text{K} = 2^{18}$ words, so it has 18 address lines. The lower 16 lines go to all chips in parallel. The upper 2 lines go to a $2 \times 4$ decoder. Each output of the decoder enables one row of 2 chips. Only that row works at a time. The two chips of the row give the upper and lower bytes of the 16-bit word.

 A17 A16 --> [2x4 decoder] -> CS of row 0..3
 A15..A0 --> all 8 chips
 Row k : [64Kx8 chip] [64Kx8 chip] -> D15..D8, D7..D0

The cache is small, so the memory block that goes into a cache line must be decided by a rule. This rule is the mapping technique. To compare the three, take a 16-bit address, a block of 4 words, and a cache of 256 lines.

i. Direct mapping

Each memory block goes to one fixed cache line:

$$\text{line} = \text{block number} \bmod 256$$

The address has three fields: tag, line and word. The word field has 2 bits, the line field has 8 bits and the tag has the remaining bits:

$$16 - 8 - 2 = 6 \text{ bits}$$

The line field selects the cache line, and its stored tag is compared with the tag of the address. If they are equal, it is a hit. This needs only one comparator and no replacement rule, so it is simple and fast. But blocks that map to the same line replace each other again and again, so the hit ratio can be poor.

ii. Associative mapping

A memory block can be placed in any cache line. The address has only a tag and a word field. Here the tag has $16 - 2 = 14$ bits and the word has 2 bits. The tag is compared with the tags of all 256 lines at the same time, using associative memory. This is the most flexible and gives the highest hit ratio, because there are no conflict misses. But it needs 256 comparators, so it is costly and slow, and it needs a replacement algorithm such as LRU or FIFO.

iii. Set-associative mapping

The lines are grouped into sets. A block maps to one fixed set, but it can go to any line in that set. For a 4-way cache, there are $256/4 = 64$ sets. The set field has 6 bits, the word field has 2 bits and the tag has

$$16 - 6 - 2 = 8 \text{ bits}$$

Only the 4 tags of one set are compared. It reduces conflict misses and costs less than the associative method. A replacement rule is needed only inside the set.

2D organization

In 2D organization, the memory cells are arranged as an array in which each row is one word. A single decoder takes all $n$ address bits and activates one of the $2^n$ word lines. Then all the bits of that word are read or written together.

 Address (n bits) --> [ n to 2^n decoder ] --> word lines
                                                 |
                                       [ cell array: 2^n words ]
                                                 |
                                             data bits

Advantages: the structure is simple, the design is easy, and a whole word is accessed at once, so it is fast for small memories. Disadvantages: the decoder needs $2^n$ output lines. For $64\text{K}$ words, that is 65536 lines and gates. The decoder is large, costly and slow, so it is unsuitable for big memories.

2 1/2D organization

In 2 1/2D organization the cells are arranged in a square-like array. The address is split into a row part and a column part. A row decoder selects one row and a column decoder (with a multiplexer) selects one column. The cell at the crossing is accessed.

 Row address (n/2)  --> [ row decoder ] --> rows
                                              |
                                        [ cell array ]
                                              |
 Col address (n/2)  --> [ column decoder / mux ] --> data

For $64\text{K} \times 1$ bits, the array is $256 \times 256$. Each decoder has 256 outputs, so the total is

$$256 + 256 = 512$$

instead of 65536 in 2D.

Advantages: the decoder size is very small, so the cost and area are low. It suits large chips, and refresh of a whole row is easy for DRAM. Disadvantages: two decoding steps are needed, so the access control is a little more complex. One cell is selected at a time per array, so several arrays must be used in parallel to get a wider word.

I/O interface

An I/O interface is the hardware circuit between the CPU buses and an I/O device. It contains registers (data, status and control), an address decoder, and timing and interrupt logic. The CPU reads and writes these registers to control the device.

Functions of an I/O interface

• Device selection: it decodes the address on the address bus and selects the correct device.
• Data buffering: it holds data in a register so that the fast CPU and the slow device can each work at their own speed.
• Data conversion: it changes the format of the data, for example parallel to serial and serial to parallel.
• Signal conversion: it matches the voltage levels and the timing of the device to those of the CPU.
• Control and timing: it gives commands to the device, and makes the read, write and handshake signals in the right order.
• Status reporting: it tells the CPU if the device is ready, busy or in error.
• Interrupt generation: it sends an interrupt request when the device needs service.
• Error detection: it can check for parity or framing errors in the data.

 CPU buses          I/O interface           Device
 Data    <==>   [data buffer      ]  <==>   data
 Address  ==>   [address decoder  ]
 Control <==>   [control / status ]  <==>   signals
 Interrupt <==  [interrupt logic  ]

Why an interface is needed

The CPU and the I/O devices are very different, so a direct connection is not possible.

Devices also differ from each other in the form of data and the operations they accept. Without an interface, the CPU would have to know the details of each device and would waste time waiting for slow ones. An interface gives the CPU one simple and uniform way to deal with every device. It also protects the CPU from the electrical and timing problems of the device.

Serial communication sends the bits of data one after another over a single line. For the receiver to understand the bits, it must know where each bit and character starts and ends. There are two ways to do this.

Synchronous communication

The sender and the receiver work with the same clock. Either the clock is sent on a separate line, or it is recovered from the data signal. Data is sent in large blocks (frames), which start with one or more synchronising characters (SYN) and end with an end marker. There are no start and stop bits for each character. Examples are the HDLC and SDLC protocols, SPI and Ethernet.

Asynchronous communication

The sender and the receiver have no common clock. Each character is sent in its own frame, with a start bit (0) in front and one or two stop bits (1) at the end. A parity bit may be added. The receiver synchronises on the falling edge of each start bit and reads the following bits at the agreed baud rate. Examples are the RS-232 serial port, a UART and a keyboard link.

 Idle  Start  D0 D1 D2 D3 D4 D5 D6 D7  Parity  Stop  Idle
 ‾‾‾‾|_____|   data bits (8)              |‾‾‾‾‾|‾‾‾

For example, to send the character "A" (ASCII 01000001) with one start bit, 8 data bits and one stop bit, the frame is 10 bits long. Only 8 of these carry data.

Differences

In short, synchronous communication is better for fast, steady transfer of large amounts of data, and asynchronous communication is better for slow, irregular transfers such as typing on a keyboard.

Concept of an interrupt

An interrupt is a signal that makes the CPU stop its current program for a while, run a special routine called the interrupt service routine (ISR), and then go back to the program. It lets the CPU respond quickly to events such as a key press, a disk finishing, or an error, without wasting time in checking for them again and again.

When the CPU accepts an interrupt, it completes the current instruction. It saves the program counter and the flags on the stack. Then it loads the address of the ISR into the program counter. At the end, a return instruction restores the saved values.

Interrupt hardware

The hardware has the following parts.

• Interrupt request lines: each device has a line (INTR) to the CPU. Many devices can share one line by an OR connection.
• Interrupt flip-flop (mask): it enables or disables interrupts. The CPU can set it by the EI and DI instructions.
• Interrupt controller: a chip such as the Intel 8259 takes requests from many devices, decides the priority, and sends the vector number to the CPU.
• Interrupt acknowledge (INTA): the CPU sends this signal to tell the device that its request is accepted. The device then puts its vector on the data bus.
• Priority circuit: a daisy chain connects the devices in series, so the one nearest to the CPU has the highest priority. A parallel priority encoder can also be used.

Types of interrupts

Hardware interrupts come from outside the CPU. Maskable interrupts (INTR) can be disabled by the program. The non-maskable interrupt (NMI) cannot be disabled and is used for serious events such as a power failure.

Software interrupts are caused by an instruction in a program, such as INT n. They are used to call operating system services.

Exceptions (traps) are raised by the CPU itself when an instruction has a problem, for example a divide by zero, an overflow, an illegal opcode or a page fault.

Interrupts may also be vectored, where the device gives the address of the ISR, or non-vectored, where the CPU jumps to one fixed address and polls the devices to find the cause.

When several interrupts come together, the one with the highest priority is served first. The NMI and exceptions usually come before the ordinary device interrupts.

Working of DMA

In Direct Memory Access, an I/O device exchanges a block of data with main memory without the CPU copying each word. The CPU sets up the transfer and then does other work. The steps in the working are as follows.

The CPU writes the starting memory address, the number of words and the direction into the DMA controller. The device then raises a DMA request. The controller sends a bus request to the CPU. The CPU finishes its current cycle, releases the buses and sends a bus grant. The controller puts the address on the address bus and sends the memory and device control signals, and one word moves directly between the device and memory. The controller increases the address and decreases the count. This repeats until the count is zero. At that point the controller returns the bus to the CPU and sends an interrupt to say that the transfer is complete.

The DMA controller

The controller has these main parts:

• Address register: it holds the address of the next memory word.
• Word count register: it holds the number of words still to be moved.
• Control register: it holds the direction and the mode (burst or cycle stealing).
• Data buffer: it connects the controller to the data bus.
• Bus request and bus grant lines: these connect it to the CPU for taking the buses.
• DMA request and acknowledge lines: these connect it to the I/O device.

The CPU can read and write these registers through the register select input, in the same way as for any other interface.

Advantages over other I/O methods

The main advantages of DMA are that it gives the highest data rate, since words are not routed through the CPU, and it frees the CPU for other tasks. It has far less overhead than interrupts because only one interrupt is used for a complete block. Its disadvantages are the extra hardware and the need to share the memory bus, which can slow the CPU a little during the transfer.