DMA (Direct Memory Access) Explained With Block Diagram: Registers, Bus Signals and Transfer Modes

"Explain DMA with a block diagram" is one of the most predictable questions in the Input Output Organization unit of TU BSc CSIT Computer Architecture (CSC213), and it also appears in Microprocessor (CSC167) and in the BIT paper on Microprocessor and Computer Architecture (BIT151). The answer needs four things: the reason DMA exists, the block diagram of a DMA controller, the sequence of signals during a transfer, and the transfer modes. Most students draw the diagram and stop there, which is a 5-mark answer to a 10-mark question.

This article walks through each part. The unit notes and solved past questions are on the Input Output Organization notes page.

Why DMA exists

There are three ways a computer can move data between an I/O device and memory. Under programmed I/O the CPU executes a loop that reads each word from the device and writes it to memory, and it can do nothing else while waiting. Under interrupt-driven I/O the device interrupts the CPU when a word is ready, which frees the CPU between words but still costs an interrupt and several instructions per word.

For a fast device such as a disk, which delivers thousands of words in a burst, both methods waste the processor. Direct memory access removes the CPU from the data path entirely. A separate hardware unit, the DMA controller, takes control of the system bus and moves a whole block between the device and memory directly. The CPU only sets up the transfer at the start and is interrupted once at the end.

Block diagram of a DMA controller

In words, for the answer sheet: draw the CPU, main memory and the peripheral device along the top, all connected to the system bus, which carries address lines, data lines and the control lines RD and WR. Below the bus draw the DMA controller as a box containing four registers and a control logic block.

The CPU is connected to the DMA controller by two signals: bus request (BR), from the controller to the CPU, and bus grant (BG), from the CPU to the controller. The device is connected to the controller by DMA request and DMA acknowledge. The controller has an address select and a register select input so that the CPU can program its registers like any other I/O interface, plus RD and WR lines that are bidirectional: they are inputs when the CPU programs the controller and outputs when the controller drives the bus.

Sequence of a DMA transfer

1. The CPU initialises the DMA controller by writing the starting memory address into the address register, the number of words into the word count register, and the direction and mode into the control register. It then continues with other work.
2. When the device is ready, it sends DMA request to the controller.
3. The controller asserts BR (bus request) to the CPU.
4. The CPU finishes its current bus cycle, places its address, data and control lines in the high-impedance state, and asserts BG (bus grant). The CPU has released the bus.
5. The controller places the address from its address register on the address bus, asserts RD or WR, and transfers one word directly between the device and memory. It sends DMA acknowledge to the device.
6. After each word the address register is incremented and the word count register is decremented.
7. When the word count reaches zero the controller releases BR, the CPU regains the bus, and the controller sends an interrupt to the CPU to report that the block transfer is complete.

The point to stress is that during the transfer the data never passes through the CPU. The CPU's only involvement is the setup at the start and the interrupt at the end.

Transfer modes

A 5-mark question often asks for burst versus cycle stealing alone. Burst gives the fastest transfer; cycle stealing gives the best CPU utilisation.

DMA and interrupts: the difference

Students sometimes confuse the two. An interrupt is a signal that makes the CPU stop its current program and run a service routine; the data is still moved by instructions the CPU executes. DMA moves the data in hardware without instructions; the interrupt is used only once, at the end of the block, to tell the CPU the job is done. Interrupt-driven I/O is appropriate for slow character devices such as a keyboard; DMA is appropriate for fast block devices such as a disk or a network card.

In the 8085 and 8237

The Microprocessor paper asks the same question in the language of the 8085, where the bus request and grant lines are called HOLD and HLDA. A device asserts HOLD; the 8085 completes the current machine cycle, tri-states its address, data and control buses, and asserts HLDA; the DMA controller then owns the bus until it removes HOLD. The Intel 8237 is the standard DMA controller studied with the 8085: it has four independent channels, each with its own current address register and current word count register, a priority logic that decides which channel is served first, and the same request and acknowledge handshake with each device. Notes for that paper are on the CSC167 Microprocessor page.

A 10-mark answer outline

1. The problem with programmed and interrupt-driven I/O for fast devices (two sentences) and the definition of DMA.
2. Block diagram, drawn with the CPU, memory, device, system bus and the DMA controller showing its address, word count, control and data registers plus control logic, with the BR and BG lines to the CPU and DMA request and acknowledge lines to the device.
3. The register functions, one line each.
4. The transfer sequence in the seven steps above.
5. The transfer modes table, with burst versus cycle stealing explained.
6. One sentence relating DMA to interrupts, or to HOLD and HLDA if the paper is Microprocessor.

Points 2, 4 and 5 are where the marks are. If the question is worth 5, draw the diagram, give the register functions and the sequence in four or five lines, and name the two main modes.

BIT students will find the matching unit at Input Output and Data Transfer in BIT151. The solved past questions on the CSC213 Computer Architecture page show how the DMA question has been worded in previous years.