Microprocessor and Block Diagram of 8085

(a) What is a Microprocessor?

A microprocessor is a programmable, single-chip VLSI (Very Large Scale Integration) device that functions as the Central Processing Unit (CPU) of a computer system. It integrates the functions of the ALU (Arithmetic and Logic Unit), Control Unit, and registers onto a single integrated circuit.

It performs three fundamental operations:

• Fetch - retrieves instructions from memory
• Decode - interprets the instruction
• Execute - carries out the required operation

Example: Intel 8085 is an 8-bit microprocessor introduced in 1976, operating at 3-5 MHz clock speed, with a 16-bit address bus capable of addressing 64 KB of memory.

(b) Block Diagram of 8085 Microprocessor

Block Diagram

+----------------------------------------------------------+
|                    8085 MICROPROCESSOR                   |
|                                                          |
|  +----------------+        +-------------------------+  |
|  | Interrupt      |        |   Timing & Control Unit |  |
|  | Control        |        |   (RD', WR', ALE, IO/M')|  |
|  | TRAP,RST7.5    |        +-------------------------+  |
|  | RST6.5,RST5.5  |                   |                  |
|  | INTR           |        +-------------------------+  |
|  +----------------+        | Instruction Register &  |  |
|                            | Decoder                 |  |
|  +----------------+        +-------------------------+  |
|  | Serial I/O     |                   |                  |
|  | Control        |    +--------------+-----------+      |
|  | SID / SOD      |    |    Internal 8-bit Bus    |      |
|  +----------------+    +--------------+-----------+      |
|                                       |                  |
|  +------------+  +--------+  +--------+--------+        |
|  | Accumulator|  |  Flag  |  | Register Array  |        |
|  |  (8-bit)   |  | Reg.   |  | B, C, D, E, H,L |        |
|  +------------+  |S,Z,AC, |  | (8-bit each)    |        |
|        |         |P, CY   |  +--------+--------+        |
|        v         +--------+           |                  |
|  +------------+                       |                  |
|  |    ALU     |<----------------------+                  |
|  | (Arith &   |                                          |
|  |  Logic)    |                                          |
|  +------------+                                          |
|                                                          |
|  +-------------------+   +---------------------------+  |
|  | Program Counter   |   | Stack Pointer (SP)        |  |
|  | (PC) - 16 bit     |   | 16-bit                    |  |
|  +-------------------+   +---------------------------+  |
|                                                          |
|  +-------------------+   +---------------------------+  |
|  | Address Buffer    |   | Data/Address Buffer       |  |
|  | A8 - A15 (8-bit)  |   | AD0 - AD7 (Multiplexed)   |  |
|  +-------------------+   +---------------------------+  |
|          |                          |                    |
+----------|--------------------------|--------------------+
           |                          |
     16-bit Address Bus          8-bit Data Bus
     (A0 - A15)                  (D0 - D7)

Explanation of Each Component

A. Accumulator (A Register)

• An 8-bit special purpose register.
• Stores one operand before an ALU operation and holds the result after the operation.
• It is the most frequently used register in all data processing tasks.

B. ALU (Arithmetic and Logic Unit)

• Performs all arithmetic operations: addition, subtraction, increment, decrement.
• Performs all logical operations: AND, OR, XOR, complement, rotate.
• Receives data from the Accumulator and Temporary Register.
• Result is stored back in the Accumulator.

C. Flag Register (Status Register)

• A 5-bit register containing condition flags set or reset based on ALU results.

D. Register Array (General Purpose Registers)

• Contains six 8-bit registers: B, C, D, E, H, L.
• Can be used individually (8-bit) or as register pairs (BC, DE, HL) for 16-bit operations.
• The HL pair is most commonly used as a memory pointer.

E. Program Counter (PC)

• A 16-bit register that always holds the memory address of the next instruction to be fetched.
• It is automatically incremented after each instruction fetch, ensuring sequential execution.

F. Stack Pointer (SP)

• A 16-bit register that points to the top of the stack in RAM memory.
• Used during PUSH, POP, CALL, and RET operations.
• Stack grows downward in memory (SP decrements on PUSH).

G. Timing and Control Unit

• The brain of the microprocessor that generates all timing and control signals.
• Key signals generated:

H. Instruction Register and Decoder

• The Instruction Register (IR) is an 8-bit register that holds the opcode fetched from memory.
• The decoder interprets that opcode and informs the timing and control unit which sequence of control signals to generate.
• The IR is not accessible to the programmer.

I. Temporary Register

• An 8-bit register that holds the second operand of an ALU operation.
• It is used internally by the processor only, and is transparent to the programmer.

J. Interrupt Control

• Handles the five hardware interrupts of the 8085: TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.
• TRAP is non maskable and has the highest priority, INTR has the lowest and is acknowledged through the INTA signal.
• On accepting an interrupt the processor saves the program counter on the stack and branches to the corresponding vector location.

K. Serial Input Output Control

• Provides SID (Serial Input Data) and SOD (Serial Output Data) lines for one-bit serial communication.
• SID is read by the RIM instruction and SOD is written by the SIM instruction.

L. Increment / Decrement Address Latch

• A 16-bit circuit that increments or decrements the contents of the PC or SP.
• It is what advances the program counter after a fetch and adjusts the stack pointer during PUSH and POP.

M. Address Buffer and Address / Data Buffer

• The address buffer drives the higher order address lines A8 to A15.
• The address/data buffer drives the multiplexed lines AD0 to AD7, which carry the lower byte of the address during the first clock state of a machine cycle and the data byte afterwards.
• The ALE signal is used by an external latch (such as the 74LS373) to hold the lower address byte while the same lines are reused for data.

Conclusion

The 8085 is an 8-bit microprocessor with a 16-bit address bus, so it can address 64 KB of memory, and its internal organisation splits neatly into three parts: the arithmetic group (accumulator, ALU, temporary register, flags), the register and address group (B to L, PC, SP, increment/decrement latch, buffers) and the control group (instruction register and decoder, timing and control unit, interrupt and serial control). All three are tied together by the internal 8-bit data bus, and the timing and control unit sequences them so that every instruction is completed as a fetch, decode and execute cycle.

Micro-program and Micro-instruction | FETCH Routine

Note: Reference notes were not available for this topic. The answer below is based on standard Computer Organization and Architecture curriculum as taught in TU BSc CSIT (Morris Mano's Computer Organization approach).

(a) Micro-program and Micro-instruction

Micro-instruction

A micro-instruction is a single word stored in the control memory that specifies one or more micro-operations to be performed by the hardware in one clock cycle.

• Each micro-instruction contains a set of bits that directly control the data path operations (register transfers, ALU operations, bus signals, etc.)
• It may also contain a field specifying the address of the next micro-instruction to be fetched.

Format of a Micro-instruction (typical):

Where:

• F1, F2, F3 - Micro-operation fields
• CD - Condition for branching
• BR - Branch type
• AD - Address field (next micro-instruction address)

Micro-program

A micro-program is a sequence (program) of micro-instructions stored in a special high-speed memory called control memory (CM) or control store.

• It is written by the computer designer (not the user) to implement the instruction set of the machine.
• The control memory is typically a ROM (Read Only Memory).
• Each machine language instruction corresponds to a micro-routine (a set of micro-instructions).
• The process of using micro-programs to implement the control unit is called microprogramming.

Key Points:

(b) Symbolic Micro-program for FETCH Routine

Background

In a basic computer (Morris Mano model), the instruction cycle begins with the FETCH routine, which:

1. Reads the instruction from memory at the address given by the Program Counter (PC)
2. Increments the PC
3. Decodes the instruction

The control memory uses symbolic notation where each line represents one micro-instruction.

Registers Used

Symbolic Micro-program for FETCH Routine

Label    |  Micro-operations          |  CD  |  BR  |  AD
---------|----------------------------|------|------|--------
FETCH:   |  AR <- PC                  |  U   |  JMP | NEXT
         |  DR <- M[AR], PC <- PC + 1 |  U   |  JMP | NEXT
         |  IR <- DR(0-10),           |  U   |  MAP | 0000000
         |  AR <- DR(11-15)           |      |      |

Explanation of Each Step

Step 1: AR <- PC

• The content of the Program Counter is transferred to the Address Register.
• This sets up the memory address from which the instruction will be fetched.
• CD = U (Unconditional), BR = JMP (go to next address)

Step 2: DR <- M[AR], PC <- PC + 1

• Memory is read: the instruction at address AR is loaded into the Data Register (DR).
• Simultaneously, the PC is incremented to point to the next instruction.
• These two micro-operations happen in parallel in one clock cycle.

Step 3: IR <- DR(0-10), AR <- DR(11-15)

• The opcode portion of the instruction (bits 0-10) is loaded into the Instruction Register (IR).
• The address portion (bits 11-15) is loaded into the Address Register (AR).
• BR = MAP: The next address is determined by mapping the opcode to the appropriate micro-routine in control memory.
• This effectively decodes the instruction and branches to the correct execute routine.

Flow Diagram

START
  |
  v
AR <-- PC                        (Point to instruction)
  |
  v
DR <-- M[AR], PC <-- PC+1        (Read instruction, advance PC)
  |
  v
IR <-- DR(opcode), AR <-- DR(addr)  (Decode instruction)
  |
  v
MAP to Execute Routine           (Branch based on opcode)

Summary Table

The FETCH routine is common to all instructions and is always executed at the beginning of every instruction cycle before the specific execute routine runs.

Direct Memory Access (DMA)

Definition

DMA (Direct Memory Access) is a memory access technique that allows I/O devices to transfer data directly to or from main memory without the continuous involvement of the CPU. The CPU only initiates the transfer; the actual data movement is handled by a dedicated hardware unit called the DMA Controller (DMAC).

Note: No specific curriculum notes were found for this topic; the answer is based on standard computer organization principles consistent with TU BSc CSIT syllabus.

Role of DMA Controller in Data Transfer

The DMA controller acts as an intermediary between the I/O device and main memory. Its role can be explained through the following steps:

Step-by-Step Operation

Modes of DMA Transfer

• Burst Mode: DMA transfers an entire block of data at once; CPU is halted during the entire transfer.
• Cycle Stealing Mode: DMA steals one bus cycle at a time from the CPU; CPU is slowed but not halted.
• Transparent Mode: DMA transfers data only when the CPU is not using the bus; slowest but no CPU interference.

Advantages of DMA

• Frees the CPU from managing data transfer byte by byte.
• Faster data transfer compared to programmed I/O or interrupt-driven I/O.
• Suitable for high-speed devices like disk drives, graphics cards, and network interfaces.

Summary Diagram

CPU --> Initializes DMAC (address, count, direction)
DMAC --> Requests Bus --> CPU Grants Bus
DMAC --> Transfers Data (I/O Device <--> Memory)
DMAC --> Sends Interrupt to CPU on Completion
CPU --> Resumes Normal Work

In essence, the DMA controller offloads the data transfer task from the CPU, making the system more efficient by allowing the CPU and I/O operations to proceed concurrently.

Booth's Multiplication Algorithm: (15) × (−13)

STEP 1: EXTRACT - Given Data

• Multiplicand = 15
• Multiplier = −13
• Method: Booth's algorithm, 2's complement

We need enough bits to represent both operands and their negatives in 2's complement.

• $+15 = 01111$ needs 5 bits, but $+15$ in signed form requires a leading 0, so minimum is 5 bits.
• $-13$: magnitude 13 = $1101$, needs 5-bit signed form $10011$.

5 bits suffices for both.

Binary (5-bit 2's complement):

Check −13: $+13 = 01101$, invert $= 10010$, +1 $= 10011$ ✓ Check −M: $01111$ invert $= 10000$, +1 $= 10001$ ✓

STEP 2: SOLVE

Initialize: A = $00000$, Q = $10011$, Q₋₁ = 0, count = 5

Rules:

• $Q_0Q_{-1}=10$: A = A − M, then ARS
• $Q_0Q_{-1}=01$: A = A + M, then ARS
• $00$ or $11$: only ARS

Let me carefully redo the ARS steps to be precise (ARS shifts A,Q,Q₋₁ right, sign bit of A preserved):

Step 1: A=$00000$, subtract M: A=$00000+10001=10001$. ARS of A=$10001$ Q=$10011$ Q₋₁=0:

• New A = $11000$, new Q = $11001$, Q₋₁ = 1 ✓

Step 2: $Q_0Q_{-1}=11$ → ARS only. ARS of A=$11000$ Q=$11001$ Q₋₁=1:

• New A = $11100$, new Q = $01100$, Q₋₁ = 1 ✓

Step 3: $Q_0Q_{-1}=01$ → A=A+M = $11100+01111 = 101011$, keep 5 bits: $01011$. ARS of A=$01011$ Q=$01100$ Q₋₁=1:

• New A = $00101$, new Q = $10110$, Q₋₁ = 0 ✓

Step 4: $Q_0Q_{-1}=00$ → ARS only. ARS of A=$00101$ Q=$10110$ Q₋₁=0:

• New A = $00010$, new Q = $11011$, Q₋₁ = 0 ✓

Step 5: $Q_0Q_{-1}=10$ → A=A−M = $00010+10001 = 10011$. ARS of A=$10011$ Q=$11011$ Q₋₁=0:

• New A = $11001$, new Q = $11101$, Q₋₁ = 1 ✓

Final Result

$$\text{Result} = A ,|, Q = 11001,11101$$

Note: the concatenated 10-bit result is $1100111101$.

Convert (10-bit 2's complement): MSB = 1 → negative. Invert $1100111101 → 0011000010$, add 1 $→ 0011000011 = 195$.

$$\boxed{15 \times (-13) = -195}$$

Verification: $15 \times 13 = 195$, so $15 \times (-13) = -195$ ✓

Addressing Modes in 8085 Microprocessor

Definition

Addressing mode refers to the way in which the operand (data) of an instruction is specified or accessed. It defines the method used by the CPU to identify the location of the data to be operated upon.

Types of Addressing Modes in 8085

The 8085 microprocessor supports the following addressing modes:

1. Immediate Addressing Mode

• The operand (data) is directly specified in the instruction itself.
• The data follows immediately after the opcode in memory.
• Example:
  View full

  MVI A, 25H   ; Load 25H directly into accumulator
  LXI H, 2050H ; Load 2050H into HL pair
  

2. Register Addressing Mode

• The operand is stored in a register, and the instruction specifies that register.
• Data is transferred between registers.
• Example:

  MOV A, B   ; Copy contents of register B to A
  ADD C      ; Add contents of register C to accumulator
  

3. Direct Addressing Mode

• The 16-bit memory address of the operand is directly given in the instruction.
• The CPU directly accesses that memory location.
• Example:
  View full

  LDA 2050H   ; Load data from memory address 2050H into A
  STA 3000H   ; Store accumulator content at address 3000H
  

4. Indirect Addressing Mode (Register Indirect)

• The address of the operand is stored in a register pair (usually HL, BC, or DE).
• The register pair acts as a pointer to the memory location.
• Example:
  View full

  MOV A, M   ; M refers to memory location pointed by HL pair
  LDAX B     ; Load accumulator with data at address in BC pair
  

5. Implicit (Implied) Addressing Mode

• The operand is implicitly defined by the instruction itself; no address or data needs to be specified separately.
• The instruction operates on a fixed, implied register (usually the accumulator).
• Example:
  View full

  CMA    ; Complement the accumulator (A is implied)
  RAL    ; Rotate accumulator left (A is implied)
  

Summary Table

Note: The reference notes were not available for this topic. The above answer is based on standard 8085 microprocessor curriculum as taught in BSc CSIT, consistent with Tribhuvan University syllabus.