Digital Logic · Unit 5 · 8 hrs
Combinational Logic with MSI and LSI
Exam-focused notes for Combinational Logic with MSI and LSI (Digital Logic, CSC116): what the TU syllabus asks and how it has actually been tested, with 15 solved past questions from this unit.
What this unit covers
- Binary Parallel Adder and Subtractor
- Decimal Adder
- Magnitude Comparator
- Decoders and Encoders
- Multiplexers
- Read-only-Memory (ROM)
- Programmable Logic Array (PLA)
- Programmable Array Logic (PAL)
Multiplexers
What is Multiplexer. Design 8 to 1 Multiplexer with low level Multiplexers. [5]
--- A Multiplexer (MUX) is a combinational circuit that accepts input from 2^n input lines and gives the output on a single output line. The selection of a particular input line is controlled by a set of selection lines. Generally, there are: - 2^n input li...
Full solved answer →Question
Implement the Boolean function $F(P,Q,R,S)=\sum(3,4,6,8,9,14)$ using:
a. 8 to 1 multiplexer b. PLA c. Decoder
[4+2+2+2]
- Function: $F(P,Q,R,S) = \sum m(3,4,6,8,9,14)$ - 4 variables: P (MSB), Q, R, S (LSB) - Implement using: (a) 8-to-1 MUX, (b) PLA, (c) Decoder m P Q R S F ------------------ 0 0 0 0 0 0 1 0 0 0 1 0 2 0 0 1 0 0 3 0 0 1 1 1 4 0 1 0 0 1 5 0 1 0 1 0 6 0 1 1 0 1 ...
Full solved answer →Implement $F = \Sigma(1,4,5,7)$ using a. Multiplexer b. Decoder c. PLA [10]
- Function: $F(A,B,C) = \Sigma(1,4,5,7)$ - 3 variables: A (MSB), B, C (LSB) - Minterms where F = 1: 1, 4, 5, 7 A B C Minterm F --------------------- 0 0 0 m0 0 0 0 1 m1 1 0 1 0 m2 0 0 1 1 m3 0 1 0 0 m4 1 1 0 1 m5 1 1 1 0 m6 0 1 1 1 m7 1 --- Select lines: $S...
Full solved answer →Implement F using:
a. Multiplexer $$F = \sum(0,2,3,4,7)$$
b. Decoder
c. PLA[4+3+3]
- Function: $F(A,B,C) = \sum m(0, 2, 3, 4, 7)$ - Number of variables: 3 (since minterms range 0-7), variables A (MSB), B, C (LSB) - Required implementations: - a. Multiplexer [4 marks] - b. Decoder [3 marks] - c. PLA [3 marks] Truth Table: Min A B C F -----...
Full solved answer →Decoders and Encoders
What is decoder? Describe the 3 to 8 line decoder circuit. [5]
A decoder is a combinational circuit that converts information of n input lines to a maximum of 2^n unique output lines. The purpose of a decoder is to generate one or more minterms of the n input variables. If any n-bit decoded information has unused or do...
Full solved answer →Write short notes on: Encoder, Error detection codes [5]
--- An encoder is a combinational logic circuit that performs the reverse operation of a decoder. - It has 2^n or fewer input lines and generates n output lines - The output lines generate the binary code corresponding to the active input - Only one input i...
Full solved answer →What is decoder circuit? Design 3 to 8 decoder circuit. [5]
--- A decoder is a combinational logic circuit that converts n input lines into a maximum of 2ⁿ output lines. It detects or "decodes" a specific binary code on its inputs and activates exactly one output line corresponding to that binary combination. - It h...
Full solved answer →Write short notes on (any two): State Diagram, Encoder, Parallel Adder [5]
--- A State Diagram is a graphical representation used to describe the behavior of a sequential circuit. It shows all possible states of the circuit and the transitions between those states based on input conditions. Component Description ------------------...
Full solved answer →Implement the following function F using:a. Decoderb. Multiplexerc. PLA[4+2+2+2]
The problem statement says: "Implement the following function F using: a. Decoder, b. Multiplexer, c. PLA [4+2+2+2]" The actual Boolean function F is NOT provided in the question text. No minterm list, no algebraic expression, no truth table, and no LaTeX a...
Full solved answer →Implement half adder using 2-4 decoders. [5]
A half adder has two inputs (A, B) and two outputs (Sum, Carry). Truth Table: A B Sum (S) Carry (C) -------------------------- 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Boolean Expressions (Sum of Minterms): $$S = A \oplus B = A'B + AB' = \sum m(1, 2)$$ $$C = AB = \s...
Full solved answer →Design the priority encoder circuit. [5]
A priority encoder is a combinational circuit that accepts multiple inputs and generates a binary code corresponding to the highest priority active input. If two or more inputs are active simultaneously, the input with the highest priority (highest index) t...
Full solved answer →Read-only-Memory
Differentiate between ROM and PLA. Explain different types of ROM. [5]
--- Feature ROM (Read Only Memory) PLA (Programmable Logic Array) --------- Full Form Read Only Memory Programmable Logic Array Structure Fixed AND array + Programmable OR array Programmable AND array + Programmable OR array AND Plane Fixed (all minterms ar...
Full solved answer →Magnitude Comparator
Differentiate between PLA and PAL. Explain 4-bit magnitude comparator. [5]
--- Feature PLA (Programmable Logic Array) PAL (Programmable Array Logic) --------- AND Array Programmable Programmable OR Array Programmable Fixed Flexibility More flexible (both arrays programmable) Less flexible (only AND array programmable) Complexity M...
Full solved answer →Programmable Logic Array
Implement the following functions using PLA:
$w(A,B,C,D)=\sum(7,12,13)$
$x(A,B,C,D)=\sum(7,8,9,10,11,12,13,14,15)$
$y(A,B,C,D)=\sum(0,2,3,4,5,6,7,8,10,11,15)$
$z(A,B,C,D)=\sum(1,2,8,12,13)$
[10]
Four 4-variable functions (A = MSB, D = LSB): - $w(A,B,C,D) = \sum(7,12,13)$ - $x(A,B,C,D) = \sum(7,8,9,10,11,12,13,14,15)$ - $y(A,B,C,D) = \sum(0,2,3,4,5,6,7,8,10,11,15)$ - $z(A,B,C,D) = \sum(1,2,8,12,13)$ AB\CD 00 01 11 10 --------------- 00 0 0 0 0 01 0 ...
Full solved answer →Programmable Array Logic
PAL Programming Table for 3-Input, 4-Output Combinational Circuit
X Y Z A B C D --------------------- 0 0 0 0 1 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 Minterms (output = 1): - $A$: 1, 2, 4, 6 - $B$: 0, 1, 3, 6, 7 - $C$: 1, 2, 4, 6, 7 - $D$: 1, 2, 3, 5, 7 A (1,...
Full solved answer →Make Unit 5 stick
Practice CSC116 with flashcards & quizzes