Synchronous vs Asynchronous Counter and 3-bit Synchronous Binary Counter Design

Part 1: Difference Between Synchronous and Asynchronous Counter

Part 2: Design of 3-bit Synchronous Binary Counter Using T Flip-Flop

Step 1: State Sequence

A 3-bit binary counter counts from 000 to 111 (0 to 7) and resets back to 000.

Let the three flip-flops be Q2 (MSB), Q1, Q0 (LSB).

Step 2: State Transition Table

Note for T Flip-Flop: T = 0 means no change (Q(next) = Q), T = 1 means toggle (Q(next) = Q') Therefore: T = Q(next) XOR Q(present)

Step 3: Derive Boolean Expressions Using K-Map

For T0:

All cells = 1, therefore:

$$\boxed{T_0 = 1}$$

For T1:

T1 = 1 only when Q0 = 1, therefore:

$$\boxed{T_1 = Q_0}$$

For T2:

T2 = 1 when Q1 = 1 and Q0 = 1, therefore:

$$\boxed{T_2 = Q_1 \cdot Q_0}$$

Step 4: Summary of Excitation Equations

$$T_0 = 1$$ $$T_1 = Q_0$$ $$T_2 = Q_1 \cdot Q_0$$

Step 5: Logic Circuit Diagram

CLK ----+----------+----------+
        |          |          |
      [T FF]     [T FF]     [T FF]
  T0=1 |     T1=Q0|    T2=Q1.Q0
        |          |          |
       Q0         Q1         Q2
        |          |          |
        +----------+          |
        |    AND --+----------+
        +----------+

Detailed Circuit:

                    +-------+         +-------+         +-------+
CLK --------------->| T  FF |-------->| T  FF |-------->| T  FF |
                    |       |         |       |         |       |
T0 = 1 ----------->| T  Q0 |    +--->| T  Q1 |    +--->| T  Q2 |
                    +-------+    |    +-------+    |    +-------+
                                 |                  |
                          Q0 ----+           Q1 & Q0 (AND) --+
                          (T1 = Q0)          (T2 = Q1.Q0)

Each T flip-flop shares the same clock line, so all three stages switch simultaneously (a true synchronous counter, unlike a ripple counter where each stage is clocked by the previous stage's output). Flip-flop Q0 toggles on every clock pulse since $T_0 = 1$, flip-flop Q1 toggles whenever Q0 is 1, and flip-flop Q2 toggles only when both Q1 and Q0 are 1, exactly reproducing the 3-bit binary counting sequence $000 \to 001 \to \cdots \to 111 \to 000$.

De-Morgan's Law and K-Map Simplification

Part 1: De-Morgan's Law

De-Morgan's Law relates the complement of a compound Boolean expression to the complements of its parts.

Theorem 1: $\overline{A + B} = \bar{A} \cdot \bar{B}$ The complement of a sum equals the product of the complements.

Theorem 2: $\overline{A \cdot B} = \bar{A} + \bar{B}$ The complement of a product equals the sum of the complements.

Truth-table verification:

Columns match, so both theorems hold.

Part 2: K-Map Simplification

Given data

• $F(P,Q,R,S)=\prod(0,1,4,5,11,14,15)$ → maxterms (cells = 0)
• $d(P,Q,R,S)=\sum(2,3,7,8,9,13)$ → don't cares (X)
• Remaining cells = 1: all ${0..15}$ minus maxterms minus don't cares
  • $F=1$ at ${6, 10, 12}$

K-map (rows PQ, cols RS)

Minterm positions:

        RS=00  01   11   10
PQ=00 |  m0 | m1 | m3 | m2 |
PQ=01 |  m4 | m5 | m7 | m6 |
PQ=11 | m12 |m13 |m15 |m14 |
PQ=10 |  m8 | m9 |m11 |m10 |

Filled values:

        RS=00  01   11   10
PQ=00 |  0  | 0  | X  | X  |
PQ=01 |  0  | 0  | X  | 1  |
PQ=11 |  1  | X  | 0  | 0  |
PQ=10 |  X  | X  | X  | 1  |

Note: $m_{11}$ is a don't care (it appears in the d-set), so it must not be entered as a 0.

Part 2A: SOP (group 1s using X's)

Ones at: m6, m10, m12. Don't cares available: m2, m3, m7, m8, m9, m11, m13.

Group 1 (quad): m12, m13, m8, m9

• $m8=1000,\ m9=1001,\ m12=1100,\ m13=1101$
• Constant: $P=1,\ R=0$. Q and S vary.
• Term: $P\bar R$

Group 2 (quad): m2, m3, m6, m7

• $m2=0010,\ m3=0011,\ m6=0110,\ m7=0111$
• Constant: $P=0,\ R=1$. Q and S vary.
• Term: $\bar P R$

Check coverage of the 1's:

• m6 → Group 2 ✓
• m12 → Group 1 ✓
• m10 → $1010$: not in Group 1 (needs R=0) nor Group 2 (needs P=0). NOT covered.

Cover m10 = $1010$ ($P=1,Q=0,R=1,S=0$). Available neighbours:

• m11 ($1011$, X) → pair m10,m11: $P=1,Q=0,R=1$ → $P\bar Q R$
• m8 ($1000$, X) → pair m10,m8: $P=1,Q=0,S=0$ → $P\bar Q\bar S$
• Extend to quad m8,m9,m10,m11 (all X except m10): $P=1,Q=0$ → $P\bar Q$ (best, largest group).

So use quad $m8,m9,m10,m11 = P\bar Q$, which also covers m10.

Final SOP: $$F = P\bar R + \bar P R + P\bar Q$$

(Alternatively $P\bar R + \bar P R + P\bar Q R$ if the m8/m9 quad is not reused, but $P\bar Q$ is the minimal literal choice using don't cares.)

Minimal form: $$\boxed{F_{SOP} = \bar P R + P\bar R + P\bar Q}$$

Part 2B: POS (group 0s using X's)

Zeros at maxterms: m0, m1, m4, m5, m11(? no), actual zero cells = ${0,1,4,5,11,14,15}$. Don't cares: ${2,3,7,8,9,13}$.

Zero cells: m0, m1, m4, m5, m11, m14, m15.

Group A (quad): m0, m1, m4, m5

• $0000,0001,0100,0101$: $P=0,R=0$ → $\bar P\bar R$
• Maxterm factor: $(P+R)$

Group B (quad): m11, m15, m14, and pair up):

• m14=$1110$, m15=$1111$, m11=$1011$
• m14,m15 pair: $P=1,Q=1,R=1$ → extend with m10(1010, is a 1 → cannot), with m13(1101,X) no.
• Quad m15,m14,m11,m10? m10 is a 1, so no.
• Use m14,m15 + m6,m7? m6 is 1. No.

Group the zeros:

• Group B: m14, m15 → $P=1,Q=1,R=1$; S varies → $PQR$ → factor $(\bar P+\bar Q+\bar R)$. Extend with X's: m14,m15,m10?(1), m6,m7(m6=1). Only m13(X) with m15,m14... m13=1101 differs in two bits. So m14,m15 stays a pair.
• Group C: m11 = $1011$ → pair with X's: m9(1001,X)→ m9,m11: $P=1,Q=0,S=1$ → extend m9,m11,m13,m15: m13=1101(X), m15=1111(zero) all valid → quad $P=1,S=1$ → $PS$ → factor $(\bar P+\bar S)$. This quad {m9,m11,m13,m15} covers zero m11 and m15.

Reassess minimal cover of zeros ${0,1,4,5,11,14,15}$:

• Group A $(P+R)$ covers 0,1,4,5.
• Quad {9,11,13,15} = $PS$ covers 11,15 → factor $(\bar P+\bar S)$.
• m14 = $1110$ remains. Pair m14 with m15(zero)? gives m14,m15 → $PQR$; or m14 with m10(1),m6(1) none. Use m14,m15 → $(\bar P+\bar Q+\bar R)$, or extend m14,m15,m13(X),m12(1 → no). Pair m14,m15,m11,m10? m10=1. So m14 covered by pair m14,m15 → factor $(\bar P+\bar Q+\bar R)$.

Final POS: $$\boxed{F_{POS} = (P+R)(\bar P+\bar S)(\bar P+\bar Q+\bar R)}$$

Summary

• SOP: $F = \bar P R + P\bar R + P\bar Q$
• POS: $F = (P+R)(\bar P+\bar S)(\bar P+\bar Q+\bar R)$

Common mistake: marking $m_{11}$ as a 0 in the K-map when it is a don't care in the given d-set. Treating it correctly gives the full SOP and POS results above.

A − B Using 1's Complement Method

Step 1 - Given Data

• $A = 46$ (minuend)
• $B = 35$ (subtrahend)
• Operation: $A - B$ using 1's complement.

Step 2 - Solve

Convert to 8-bit binary

$46_{10}$: $32+8+4+2 = 46 \Rightarrow 0010,1110$

$35_{10}$: $32+2+1 = 35 \Rightarrow 0010,0011$

1's complement of B (invert all bits)

$$B = 0010,0011 ;\Rightarrow; \overline{B} = 1101,1100$$

Add A and 1's complement of B

    0010 1110    (A)
  + 1101 1100    (1's comp of B)
  -----------
  1 0000 1010
  ^
  carry out = 1

End-around carry

A carry out of the MSB occurred, so add it back to the sum:

    0000 1010
  +         1
  -----------
    0000 1011

Result

$$0000,1011_2 = 8 + 2 + 1 = 11_{10}$$

Since a carry-out (end-around carry) was produced, the result is positive.

Check: $46 - 35 = 11$ ✓

Summary

D Flip Flop

Introduction

The D flip flop (Data or Delay flip flop) is a modification of the SR flip flop. It eliminates the ambiguous condition (S=R=1) by ensuring that the two inputs are always complementary. The single input D is connected directly to S and through an inverter to R, so S and R can never be equal simultaneously.

Circuit Diagram

        +-------+
    D --+---S   |
        |   NOR FF----> Q
    D --[INV]--R|
        |       |-----> Q'
   CLK -+--CLK  |
        +-------+

A more detailed gate-level circuit:

         +-----+
    D -->|     |
         | AND |----> S ---+
CLK ---->|     |           |   +-----+     Q
         +-----+           +-->| NOR |--+---->
                               |     |  |
         +-----+           +-->| NOR |--+----> Q'
    D -->|INV  |--> D' |   |   +-----+
         +-----+   |   |   |
         +-----+   v   |   |
    D'-->|     |       |   |
         | AND |----> R----+
CLK ---->|     |
         +-----+

Key point: The inverter between D and the R-input ensures R = D' and S = D at all times.

Block Diagram

        +-------------+
        |             |
   D -->|   D  FF   Q |----> Q
        |             |
 CLK -->|  CLK    Q'  |----> Q'
        |             |
        +-------------+

Characteristic Table

X = don't care

When the clock pulse is active (1):

• If D = 0, output Q becomes 0 (Reset)
• If D = 1, output Q becomes 1 (Set)

The output simply follows the D input on the active clock edge.

Characteristic Equation

$$Q(t+1) = D$$

This means the next state of the flip flop is exactly equal to the present value of input D, regardless of the current state Q(t).

Excitation Table

The required D input is simply equal to the desired next state Q(t+1).

Summary

The D flip flop is widely used in registers and memory elements because it stores exactly one bit of data and transfers it to the output on each clock pulse.

Simplification of F(A,B,C,D) = Σ(1,3,4,6,9,11,12,14) and NOR Realization

Step 1: Given Data

• Function: $F(A,B,C,D) = \sum(1,3,4,6,9,11,12,14)$
• 4 variables: A (MSB), B, C, D (LSB)
• Requirement: simplify, then realize using NOR gates only

Step 2: K-Map Plot

Minterms in binary (ABCD):

• m1 = 0001, m3 = 0011, m4 = 0100, m6 = 0110
• m9 = 1001, m11 = 1011, m12 = 1100, m14 = 1110

Let me verify placement (columns are AB, rows are CD):

• m1 (A=0,B=0,C=0,D=1): AB=00, CD=01 ✓
• m3 (0,0,1,1): AB=00, CD=11 ✓
• m4 (0,1,0,0): AB=01, CD=00 ✓
• m6 (0,1,1,0): AB=01, CD=10 ✓
• m9 (1,0,0,1): AB=10, CD=01 ✓
• m11 (1,0,1,1): AB=10, CD=11 ✓
• m12 (1,1,0,0): AB=11, CD=00 ✓
• m14 (1,1,1,0): AB=11, CD=10 ✓

Step 3: Group the 1s

Group 1 (Quad): m1, m3, m9, m11 → cells with B=0, D=1

• A varies (0,1), C varies (0,1), B=0 fixed, D=1 fixed → B'D

Group 2 (Quad): m4, m6, m12, m14 → cells with B=1, D=0

• A varies, C varies, B=1 fixed, D=0 fixed → BD'

Step 4: Simplified SOP

$$\boxed{F = B'D + BD' = B \oplus D}$$

Step 5: Convert for NOR Realization

NOR gates naturally give POS form. Group the 0s to find $F'$.

Zeros at: m0, m2, m5, m7, m8, m10, m13, m15

Group A (0s): m0, m2, m8, m10 → B=0, D=0 → B'D' Group B (0s): m5, m7, m13, m15 → B=1, D=1 → BD

$$F' = B'D' + BD$$

Complement to get POS:

$$F = (F')' = (B'D' + BD)' = (B'D')'\cdot(BD)'$$

$$F = (B + D)(B' + D')$$

Step 6: NOR Gate Implementation

For a POS expression, standard NOR realization uses a NOR-NOR structure. We write each sum term as a NOR (inverted OR) and combine.

Note the identity: $(X)(Y) = \overline{\overline{X} + \overline{Y}} = \overline{,\overline{X}\ \text{NOR}\ \overline{Y},}$... rather, express directly:

$$F = (B+D)(B'+D') = \overline{\overline{(B+D)(B'+D')}} = \overline{\ \overline{(B+D)} + \overline{(B'+D')}\ }$$

So: $$F = \overline{(B \text{ NOR } D) + (B' \text{ NOR } D')} = (B \text{ NOR } D)\ \text{NOR}\ (B' \text{ NOR } D')$$

Gate list (NOR only):

Circuit sketch:

B --------+------[G3: NOR]---+
D --------|--+---            |
          |  |               +--[G5: NOR]--> F
B --[G1:NOR B,B]=B'--[G4:NOR]--+
D --[G2:NOR D,D]=D'--

Final Answer

$$\boxed{F = B'D + BD' = B \oplus D = (B+D)(B'+D')}$$

Realized with 5 NOR gates: 2 as inverters (for B', D'), 2 for the sum terms, 1 for the final combination.

Types of Shift Registers and SIPO with Timing Diagram

Types of Shift Registers

As stated in the notes, a shift register is any register capable of shifting its binary information either to the right or to the left. It consists of a chain of flip-flops connected in cascade, with the output of one flip-flop connected to the input of the next, and all flip-flops sharing a common clock pulse.

The four different types of shift registers are:

Serial In Parallel Out (SIPO) Shift Register

Definition

In a SIPO shift register, data is entered one bit at a time serially (one bit per clock pulse) through a single input line, and all stored bits are available simultaneously at the output (parallel output) after all bits have been shifted in.

Circuit Diagram (4-bit SIPO using D Flip-Flops)

Serial                                         Parallel Outputs
Input
        +------+     +------+     +------+     +------+
SI ---->| D  Q |---->| D  Q |---->| D  Q |---->| D  Q |
        |  FF0 |     |  FF1 |     |  FF2 |     |  FF3 |
CLK --->| CLK  | --->| CLK  | --->| CLK  | --->| CLK  |
        +------+     +------+     +------+     +------+
           |            |            |            |
           Q0           Q1           Q2           Q3
        (Parallel Output Available at Q0, Q1, Q2, Q3)

• Data enters at SI (Serial Input) of FF0.
• At each clock pulse, data shifts from FF0 -> FF1 -> FF2 -> FF3.
• After 4 clock pulses, all 4 bits are available simultaneously at Q0, Q1, Q2, Q3.

Operation (Loading the 4-bit data: 1 0 1 1, MSB first)

After 4 clock pulses, Q0=1, Q1=1, Q2=0, Q3=1 are available in parallel.

Timing Diagram

CLK  : __|--|__|--|__|--|__|--|__

SI   : __|1111|0000|1111|1111|__
         (bit1)(bit2)(bit3)(bit4)

Q0   : __|1111|0000|1111|1111|__

Q1   : ______|1111|0000|1111|__

Q2   : __________|1111|0000|1111

Q3   : _______________|1111|0000

• Each bit shifts one stage to the right on every rising edge of the clock.
• After 4 clock pulses, all outputs Q0 through Q3 hold the complete 4-bit word simultaneously.

Key Characteristics of SIPO

• Input: Single serial line (1 bit per clock)
• Output: All bits available simultaneously (parallel)
• Clock pulses needed: Equal to the number of bits (n pulses for n-bit register)
• Application: Used in serial-to-parallel data conversion, communication interfaces (e.g., UART receivers)

Decoder and 3-to-8 Line Decoder

What is a Decoder?

A decoder is a combinational circuit that converts information of n input lines to a maximum of 2^n unique output lines. The purpose of a decoder is to generate one or more minterms of the n input variables. If any n-bit decoded information has unused or don't-care condition combinations, the decoder will have fewer than 2^n outputs.

3-to-8 Line Decoder

In a 3-to-8 line decoder, three inputs are converted into 8 outputs. It takes 3 input lines (A, B, C) and generates 8 output lines (D0 to D7), where each output corresponds to one unique minterm of the three input variables.

Truth Table

Boolean Expressions for Each Output

Each output is active HIGH (equals 1) for exactly one input combination:

D0 = A'B'C'    (minterm 0)
D1 = A'B'C     (minterm 1)
D2 = A'BC'     (minterm 2)
D3 = A'BC      (minterm 3)
D4 = AB'C'     (minterm 4)
D5 = AB'C      (minterm 5)
D6 = ABC'      (minterm 6)
D7 = ABC       (minterm 7)

Logic Circuit Diagram

The circuit uses 3 inverters (to generate complements A', B', C') and 8 three-input AND gates (one for each output):

        A ---+-------+--- A'(inverter)
             |
        B ---+-------+--- B'(inverter)
             |
        C ---+-------+--- C'(inverter)

A' B' C' ---> [AND] ---> D0
A' B' C  ---> [AND] ---> D1
A' B  C' ---> [AND] ---> D2
A' B  C  ---> [AND] ---> D3
A  B' C' ---> [AND] ---> D4
A  B' C  ---> [AND] ---> D5
A  B  C' ---> [AND] ---> D6
A  B  C  ---> [AND] ---> D7

Key Points

• The decoder has 3 inputs and 8 outputs (since 2^3 = 8).
• At any given time, exactly one output is HIGH and all others are LOW.
• Each output represents a unique minterm of the input variables.
• A decoder with an enable input can also function as a demultiplexer, where the enable line acts as the data input and the input lines act as select lines.