Half Adder: Derivation, Circuit, and NAND Implementation

STEP 1 - Given Data

• Inputs: two single bits $A$, $B$
• Outputs: $S$ (Sum), $C$ (Carry)
• Constraint for last part: implement using only NAND gates

No numeric data missing; this is a derivation/design problem.

STEP 2 - Solution

Truth Table

Boolean Expressions

Sum: $S = 1$ for minterms $(A=0,B=1)$ and $(A=1,B=0)$:

$$S = \bar{A}B + A\bar{B} = A \oplus B$$

Carry: $C = 1$ only when $A=1, B=1$:

$$C = A \cdot B$$

Combinational Circuit (basic gates)

A ---+----[ XOR ]---- S
     |   +--/
B ---+---+
     |    \
     +----[ AND ]---- C

• Sum = XOR gate
• Carry = AND gate

Implementation Using Only NAND Gates

NAND is a universal gate. We build XOR (Sum) and AND (Carry).

Standard XOR from NAND (4 gates):

Let $P = \overline{A \cdot B}$ (A NAND B)

$$Q = \overline{A \cdot P},\qquad R = \overline{B \cdot P}$$ $$S = \overline{Q \cdot R}$$

Verification that $S = A \oplus B$:

• $Q = \overline{A(\overline{AB})} = \overline{A}+AB\cdot\ldots$; expanding, $Q = \overline{A \cdot \overline{AB}} = A(\overline{\overline{AB}})' $. Simpler: $Q = \overline{AP} = \bar{A} + \bar{P} = \bar{A} + AB = \bar A + B$... use standard known result: this 4-NAND network yields $S = A\bar B + \bar A B = A \oplus B$. ✓

Carry: $C = A \cdot B = \overline{\overline{A \cdot B}} = \overline{P} = P \uparrow P$

So the same gate $P = A\uparrow B$ is reused; one extra NAND gives Carry.

Gate list:

NAND-only circuit:

A --+---[G1]---+--- P ---+---[G2]--- Q --+
    |          |         |               [G4]--- S
B --+          |         +--[G3]-- R ----+
    |          |          (with B)
    +----------|--[G3 input B]
               |
               P --[G5]--- C

Total: 5 NAND gates (G1 shared between Sum and Carry paths).

Summary

Total distinct gates = 5, since the NAND producing $P = \overline{AB}$ serves both outputs.

Short Notes (Any Two): Negative Logic, CMOS, EBCDIC

1. Negative Logic

Definition: In digital systems, logic levels are represented by two voltage levels. The assignment of these voltage levels to logic 0 and logic 1 defines the logic convention used.

• In Positive Logic: The higher voltage level represents logic 1 and the lower voltage level represents logic 0.
• In Negative Logic: The lower voltage level represents logic 1 and the higher voltage level represents logic 0.

Key Points:

Effect on Gates:

• A gate that functions as an AND gate in positive logic behaves as an OR gate in negative logic, and vice versa.
• This is a direct consequence of De Morgan's theorem.

Example:

• A positive logic AND gate with inputs A, B and output F:
  • F = A · B (positive logic)
  • The same physical gate in negative logic performs: F = A + B (OR operation)

Significance:

• The choice of logic convention does not change the physical hardware; it only changes the interpretation of the signals.
• Negative logic is sometimes used to simplify circuit design or to match the active-low nature of certain hardware signals.

2. CMOS (Complementary Metal Oxide Semiconductor)

Definition: CMOS is a widely used technology for constructing integrated circuits. It uses a complementary pair of p-type (PMOS) and n-type (NMOS) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) to implement logic functions.

Basic Structure:

• Every CMOS gate consists of two networks:
  • Pull-Up Network (PUN): Made of PMOS transistors, connects output to V_DD (logic 1) when active.
  • Pull-Down Network (PDN): Made of NMOS transistors, connects output to GND (logic 0) when active.
• PUN and PDN are always complementary -- when one conducts, the other does not.

CMOS Inverter (NOT Gate):

        VDD
         |
       [PMOS]  <-- Gate Input A
         |
         +----> Output F = A'
         |
       [NMOS]  <-- Gate Input A
         |
        GND

• When A = 1: NMOS ON, PMOS OFF → Output = 0
• When A = 0: NMOS OFF, PMOS ON → Output = 1

Characteristics of CMOS:

Advantages:

• Very low power dissipation -- power is consumed only during switching transitions.
• High noise immunity.
• Operates over a wide range of supply voltages (typically 3V to 15V).
• Suitable for VLSI design due to high packing density.

Applications:

• Microprocessors, memory chips (RAM, ROM), digital logic circuits, mobile devices.

3. EBCDIC (Extended Binary Coded Decimal Interchange Code)

Definition: EBCDIC is an 8-bit character encoding standard developed by IBM for use in its mainframe and midrange computer systems. The name stands for Extended Binary Coded Decimal Interchange Code.

Key Features:

Structure:

• The 8 bits are divided into:
  • 4 zone bits (higher order bits)
  • 4 numeric bits (lower order bits)
• This is an extension of the older 6-bit BCD (Binary Coded Decimal) code.

Example of EBCDIC Codes:

Comparison with ASCII:

Significance:

• EBCDIC was one of the earliest standardized character encoding systems.
• It is not compatible with ASCII, which often requires conversion when transferring data between IBM mainframes and other systems.
• Despite being largely replaced by ASCII and Unicode in modern systems, EBCDIC is still used in legacy IBM mainframe environments.

Note: Two of the above three topics are to be answered as per the question requirement (Any Two). All three are provided here for completeness.