Half Adder: Derivation, Circuit, and NOR Implementation

STEP 1 - Given Data

• Inputs: two single-bit binary values, $A$ and $B$
• Outputs: Sum $S$, Carry $C$
• Constraint: implement using only NOR gates

All required information is present in the question.

STEP 2 - Solution

Truth Table

Boolean Expressions

Sum: $S = 1$ for the minterms $(A=0,B=1)$ and $(A=1,B=0)$:

$$S = \bar{A}B + A\bar{B} = A \oplus B$$

Carry: $C = 1$ only when both inputs are 1:

$$C = A \cdot B$$

Combinational Circuit (XOR + AND)

A ──┬───────────┐
    │          [XOR]───── S = A ⊕ B
B ──┼───────────┘
    │
    ├───────────┐
    │          [AND]───── C = A·B
B ──┘───────────┘

NOR-Only Implementation

Basic NOR identities:

• $\bar{X} = X \text{ NOR } X$
• $X + Y = (X \text{ NOR } Y) \text{ NOR } (X \text{ NOR } Y)$
• $X \cdot Y = (X \text{ NOR } X) \text{ NOR } (Y \text{ NOR } Y)$

Carry $C = A \cdot B$. Using AND-from-NOR:

$$C = (A \text{ NOR } A) \text{ NOR } (B \text{ NOR } B) = \overline{\bar A + \bar B} = A\cdot B$$

Sum $S = A \oplus B$. The standard 5-gate NOR realization of XOR:

Verification of G4/G5: $\text{G4} = \overline{S}$, so $\text{G5}=\overline{\overline S}=S$. Correct.

Circuit diagram (NOR gates only):

A ─┬───────────[G1]────┬───────[G2]───┐
   │      B ────┘       │  A ───┘      │
   │                    └──[G3]────┐   ├─[G4]──[G5]── S
   │              B ───────────────┘   │  (G4 fed twice)
   │
   ├─[Ga: A NOR A = A']──┐
   │                     ├─[Gc]── C
   └─────────────────────┘
       B ─[Gb: B NOR B = B']──┘

Gate count:

• Sum: 5 NOR gates (G1-G5)
• Carry: 3 NOR gates (Ga = $\bar A$, Gb = $\bar B$, Gc = final NOR)
• G1 is shared, but counting independently: Sum = 5, Carry = 3.

Summary

A wiring trap worth knowing: one tempting XOR construction does not work. Taking:

• G4 = G1 NOR G2 = $\overline{\overline{A+B} + \bar A}$. Evaluate: $= (A+B)\cdot A = A$, not $A\bar B$.
• G5 = G1 NOR G3 = $(A+B)\cdot B = B$, not $\bar A B$.
• G6 = G4 NOR G5 = $A$ NOR $B = \overline{A+B}$, which is NOT $A\oplus B$.

So those gate assignments do not yield the XOR. The correct minimal XOR uses 5 NOR gates with the wiring shown above, giving $S = A\oplus B$ and $C = A\cdot B$.

Short Notes (Any Two): a. Positive Logic and c. ASCII

a. Positive Logic

Positive Logic is a convention used in digital systems to assign binary logic values (0 and 1) to the two voltage levels present in a circuit.

Definition:

In positive logic, the higher voltage level is assigned the logic value 1 (HIGH) and the lower voltage level is assigned the logic value 0 (LOW).

Key Points:

• It is the most commonly used logic convention in digital circuits and computers.
• Logic gates (AND, OR, NOT, etc.) are designed and analyzed based on this convention.
• The opposite convention is called Negative Logic, where the lower voltage level represents logic 1 and the higher voltage level represents logic 0.
• The same physical circuit can perform different logical operations depending on whether positive or negative logic convention is applied.

Example:

• In a TTL (Transistor-Transistor Logic) circuit, +5V = Logic 1 and 0V = Logic 0 under positive logic convention.

c. ASCII

ASCII stands for American Standard Code for Information Interchange.

Definition:

ASCII is a standard character encoding scheme used to represent text and control characters in computers and communication devices using binary numbers.

Key Features (from notes):

• ASCII uses a 7-bit code, consisting of:
  • 3 zone bits (higher order bits)
  • 4 numeric bits (lower order bits)
• Total possible combinations: 2^7 = 128 characters

Character Representation:

Example:

Additional Notes:

• ASCII is considered an improvement over the BCD code as it can represent a much wider range of characters.
• It is widely used in data communication, keyboards, and text files.
• An extended version (ASCII-8) uses 8 bits, allowing 256 characters, which includes additional special and graphical symbols.
• Another extended code, EBCDIC (Extended Binary Coded Decimal Interchange Code), is used mainly in IBM mainframe computers.