Electrical Conductivity of Semiconductors

1. Introduction to Semiconductors

A semiconductor is a material whose valence band and conduction band are partially filled with a small forbidden gap between them. It acts as a conductor at high temperature and as an insulator at low temperature. The temperature coefficient of resistance is negative (conductivity increases with temperature). Examples: Silicon (Si), Germanium (Ge).

2. Types of Semiconductors

(a) Intrinsic Semiconductor

A pure semiconductor (e.g., pure Si or Ge) where the number of electrons equals the number of holes: $$n_e = n_h = n_i$$

(b) Extrinsic (Impurity) Semiconductor

A semiconductor doped with trivalent or pentavalent impurities:

• N-type: Doped with pentavalent impurity (P, As, Sb). Free electrons are majority carriers.
• P-type: Doped with trivalent impurity (B, Al, In). Holes are majority carriers.

3. Electrical Conductivity of Semiconductors

The total electrical conductivity of a semiconductor is given by contributions from both electrons and holes:

$$\boxed{\sigma = n_e e \mu_e + n_h e \mu_h}$$

where:

• $n_e$, $n_h$ = number density of electrons and holes respectively
• $e$ = electronic charge
• $\mu_e$, $\mu_h$ = mobility of electrons and holes respectively

For an intrinsic semiconductor, $n_e = n_h = n_i$, so:

$$\sigma_i = n_i e(\mu_e + \mu_h)$$

4. Derivation of Conductivity in Terms of Impurity Ionization Energy

Setting Up the Problem

Consider an N-type extrinsic semiconductor with donor impurity concentration $N_d$. Each donor atom has an ionization energy $\Delta E$ (the energy required to free the donor electron into the conduction band).

Carrier Concentration from Statistical Mechanics

The number of electrons thermally excited into the conduction band from donor levels is determined by the Fermi-Dirac distribution. For the donor level at energy $E_d$ below the conduction band edge $E_c$:

$$\Delta E = E_c - E_d$$

At temperature $T$, the probability that a donor electron is ionized (excited to conduction band) follows Boltzmann statistics (valid when $\Delta E \gg k_BT$):

$$f(E_c) \propto \exp\left(-\frac{\Delta E}{k_B T}\right)$$

Electron Concentration

The density of electrons in the conduction band is:

$$n_e = \sqrt{N_c \cdot N_d} \exp\left(-\frac{\Delta E}{2k_B T}\right)$$

where:

• $N_c = 2\left(\frac{2\pi m_e^* k_B T}{h^2}\right)^{3/2}$ is the effective density of states in the conduction band
• $N_d$ = donor impurity concentration
• $\Delta E$ = ionization energy of the donor impurity
• $k_B$ = Boltzmann constant
• $T$ = absolute temperature

More explicitly, since $N_c \propto T^{3/2}$:

$$n_e = A \cdot T^{3/4} \exp\left(-\frac{\Delta E}{2k_B T}\right)$$

where $A$ is a constant depending on effective mass and impurity concentration.

Expression for Conductivity

Since $\sigma = n_e e \mu_e$ (for N-type, electrons are majority carriers), and mobility $\mu_e \propto T^{-3/2}$ (due to lattice scattering), we write:

$$\sigma = n_e e \mu_e$$

Substituting:

$$\boxed{\sigma = \sigma_0 , T^{-3/4} \exp\left(-\frac{\Delta E}{2k_B T}\right)}$$

where $\sigma_0$ is a pre-exponential constant that absorbs all weakly temperature-dependent terms.

Taking the natural logarithm:

$$\ln \sigma = \ln \sigma_0 - \frac{3}{4}\ln T - \frac{\Delta E}{2k_B T}$$

At low temperatures, the exponential term dominates, so:

$$\ln \sigma \approx \text{const} - \frac{\Delta E}{2k_B T}$$

This shows that a plot of $\ln \sigma$ vs $\dfrac{1}{T}$ gives a straight line with slope $-\dfrac{\Delta E}{2k_B}$, allowing experimental determination of the ionization energy.

5. Theoretical Temperature Dependence of Conductivity of an Impurity Semiconductor

The plot of $\ln \sigma$ (or $\log \sigma$) versus $1/T$ is shown below:

ln(σ)
|
|         * (saturation / extrinsic region)
|      *******
|    *         (freeze-out region)
|  *
| *  slope = -ΔE/2k_B
|*
|___________________________
        1/T (increasing →)
        (T decreasing →)

Description of the Three Regions:

Fermi Energy and Effective Mass of Aluminum

Step 1 - Given Data

Step 2 - Solve

Electron density $n$

$$n = \frac{\rho N_A Z}{M} = \frac{2.70 \times 6.022\times10^{23} \times 3}{26.98}$$

$$= \frac{4.878\times10^{24}}{26.98} = 1.808\times10^{23}\ \text{cm}^{-3} = 1.808\times10^{29}\ \text{m}^{-3}$$

Part (a) - Fermi Energy

$$E_F = \frac{\hbar^2}{2m_e}(3\pi^2 n)^{2/3}$$

Compute $3\pi^2 n$: $$3\pi^2 n = 29.608 \times 1.808\times10^{29} = 5.354\times10^{30}\ \text{m}^{-3}$$

Now $(5.354\times10^{30})^{2/3}$:

• $5.354^{1/3} = 1.7495$, so $5.354^{2/3} = 3.0608$
• $(10^{30})^{2/3} = 10^{20}$

$$(3\pi^2 n)^{2/3} = 3.061\times10^{20}\ \text{m}^{-2}$$

Prefactor: $$\frac{\hbar^2}{2m_e} = \frac{(1.055\times10^{-34})^2}{2 \times 9.109\times10^{-31}} = \frac{1.113\times10^{-68}}{1.822\times10^{-30}} = 6.109\times10^{-39}\ \text{J·m}^2$$

Therefore: $$E_F = 6.109\times10^{-39} \times 3.061\times10^{20} = 1.870\times10^{-18}\ \text{J}$$

$$E_F = \frac{1.870\times10^{-18}}{1.602\times10^{-19}} \approx 11.68\ \text{eV}$$

$$\boxed{E_F \approx 11.7\ \text{eV}}$$

Part (b) - Effective Mass

Since $n$ (hence $(3\pi^2 n)^{2/3}$) is fixed, and $E_F \propto 1/m^*$:

$$m^* = \frac{\hbar^2 (3\pi^2 n)^{2/3}}{2 E_F}$$

A neat shortcut: $$\frac{m^*}{m_e} = \frac{E_F^{\text{(theory)}}}{E_F^{\text{(exp)}}} = \frac{11.68}{12}$$

Direct calculation with $E_F = 12\times1.602\times10^{-19} = 1.922\times10^{-18}\ \text{J}$:

$$m^* = \frac{(1.055\times10^{-34})^2 \times 3.061\times10^{20}}{2 \times 1.922\times10^{-18}}$$

$$= \frac{1.113\times10^{-68} \times 3.061\times10^{20}}{3.844\times10^{-18}} = \frac{3.407\times10^{-48}}{3.844\times10^{-18}}$$

$$= 8.863\times10^{-31}\ \text{kg}$$

As a fraction of the free electron mass: $$\frac{m^*}{m_e} = \frac{8.863\times10^{-31}}{9.109\times10^{-31}} \approx 0.973$$

$$\boxed{m^* \approx 8.86\times10^{-31}\ \text{kg} \approx 0.97,m_e}$$

Summary

The results are 11.7 eV and $0.97,m_e$, using $3.055\times10^{20}$ in the intermediate step.

STEP 1 - EXTRACT: Given Data

Circuit type: Two-transistor logic gate (as described).

Stated inputs (logic levels):

• $V_A \in {0\text{ V}, 5\text{ V}}$
• $V_B \in {0\text{ V}, 5\text{ V}}$
• Common collector load resistor $R_C$
• Output $V_{out}$ taken at collector node.

Missing data note: The actual figure is not available. Without it the exact transistor type (NPN or PNP), the position of the inputs (base or emitter), and the way $R_C$ ties to the supply are all unknown, so the truth table and gate identification depend on reasoning about the unseen topology. The standard analysis for a two-input transistor gate is presented below.

STEP 2 - SOLVE

General principle for transistor logic gates

The behaviour of a two-transistor gate depends on whether the transistors are wired in series or in parallel between the output node and the reference rail:

• Transistors in SERIES (both must conduct to pull the output): gives an AND-type conduction (output pulled only when both inputs active).
• Transistors in PARALLEL (either one conducting pulls the output): gives an OR-type conduction.

For the standard textbook figure being referenced (two transistors driving a common collector resistor, inputs at the bases, output at collector), the most common configurations produce:

• Parallel NPN transistors, output at collector, pulled LOW when either conducts → NOR gate.
• Series NPN transistors → NAND gate.

Evaluating the Case Analysis

Taking the figure to use PNP transistors with the inputs at the emitters, the junction-bias reasoning carries an internal inconsistency:

• In Case (i) it claims both collector-base junctions forward biased giving current and $V_{out}$ HIGH, yet in Case (iv) it claims a symmetric situation gives $V_{out}$ LOW. The physical justification for the asymmetry is not clearly established from the stated bias conditions.

Nonetheless, taking the stated case outcomes at face value:

This truth table is HIGH only when both inputs are HIGH, which is the AND function:

$$Y = A \cdot B$$

Verified conclusion

Given only the information available (no visible figure), I cannot independently confirm the exact topology. If the transistors are arranged so that the output is active only when both inputs are HIGH, then the resulting logic is:

$$\boxed{Y = A \cdot B \quad \text{(AND gate)}}$$

The final logic result is an AND gate, as one consistent interpretation, while noting that:

1. The figure is not available for full verification.
2. The junction-bias justification (especially the Cases i against iv asymmetry) is physically weak and should be tightened. A cleaner justification for AND behaviour would be two conducting elements in series, so that current and output are enabled only when both inputs are HIGH.

Summary of logic function: The circuit performs the AND operation, output HIGH only for $A = B = 1$.

Neutron Spectroscopy: Bragg Diffraction

Step 1 - Given Data

• Interplanar spacing: $d = 0.732\ \text{Å}$
• Neutron wavelength: $\lambda = 0.1\ \text{Å}$
• Order: $n = 1$ (first order)

Step 2 - Solve

Bragg's Law:

$$2d\sin\theta = n\lambda$$

Solve for $\theta$:

$$\sin\theta = \frac{n\lambda}{2d} = \frac{1 \times 0.1}{2 \times 0.732} = \frac{0.1}{1.464} = 0.068306$$

Therefore:

$$\theta = \sin^{-1}(0.068306) = 3.915^\circ$$

$$\boxed{\theta \approx 3.92^\circ}$$

Result

The angle between the incident neutron beam and the atomic planes must be approximately $3.92^\circ$ (i.e. about $3^\circ 55'$) for first-order reflection.