RTL and TTL Logic Gates: Memory and Clock Circuits

1. RTL (Resistor-Transistor Logic) Gates

Definition

RTL (Resistor-Transistor Logic) is one of the earliest logic gate families where resistors and bipolar junction transistors (BJTs) are used to implement logic functions. The resistors are used for input coupling and the transistors act as switching elements.

Basic RTL NOR Gate Circuit

Vcc (+5V)
     |
    [Rc]
     |
     +-------- Output (Y)
     |
    [Q1]    [Q2]
     |        |
    [R1]    [R2]
     |        |
    A         B

• When either input A or B is HIGH (logic 1), the corresponding transistor saturates (turns ON), pulling output LOW.
• When both inputs are LOW, both transistors are OFF, output is pulled HIGH through Rc.
• This implements a NOR gate: Y = (A + B)'

phy118-rtl-nor-gate

Truth Table (NOR)

Characteristics of RTL

• Simple and low cost
• Slow switching speed
• High power dissipation
• Low noise immunity
• Voltage levels: Logic 0 = 0V, Logic 1 = 3.6V (approx.)

2. TTL (Transistor-Transistor Logic) Gates

Definition

TTL (Transistor-Transistor Logic) is a logic gate family where multiple-emitter BJTs are used for both input and logic functions. It replaced RTL due to higher speed and better noise immunity. TTL operates on a +5V supply.

Basic TTL NAND Gate Circuit

Vcc (+5V)
     |
    [R1]        [R3]
     |            |
     +---[Q2]----+----[Q4]---- Output (Y)
     |    |      |
    [Q1]  |     [Q3]
   /   \  |      |
  A     B [R2]  GND
           |
          GND

Key components:

• Q1: Multi-emitter input transistor (one emitter per input)
• Q2: Phase splitter transistor
• Q3, Q4: Totem-pole output stage
• R1, R2, R3, R4: Biasing resistors

Working of TTL NAND Gate

Case 1: Any input is LOW (0)

• The emitter of Q1 connected to LOW input conducts
• Q1 base-emitter junction forward biased
• Q2 and Q3 are turned OFF
• Q4 turns ON
• Output is HIGH (logic 1)

Case 2: All inputs are HIGH (1)

• All emitters of Q1 are at HIGH voltage
• Q1 operates in reverse active mode
• Q2 and Q3 turn ON (saturate)
• Q4 turns OFF
• Output is LOW (logic 0)

This implements: Y = (A.B)' (NAND function)

Truth Table (NAND)

Characteristics of TTL

3. Memory Circuit Using Logic Gates (SR Latch)

A memory circuit (latch) stores one bit of information. It can be built using NOR gates (RTL) or NAND gates (TTL).

SR Latch Using NOR Gates (RTL-based)

        S ----[NOR]---- Q
               |   \
               |    \
               +-----[NOR]---- Q'
               |   /
        R ----/

Circuit Diagram:

S ---+--[NOR Gate 1]---+--- Q
     |        ^        |
     |        |        |
     +--------+        |
                       |
R ---+--[NOR Gate 2]---+--- Q'
     |        ^        |
     |        |        |
     +--------+

More precisely:

S ----\
       [NOR1] ---- Q ----\
      /                   [NOR2] ---- Q'
Q' --/                   /
                    R ---/

Working of SR Latch

Explanation:

• When S=1, R=0: NOR1 output goes LOW (Q=0 initially), but feedback

Solution: Oscillating Block on a Spring

STEP 1 - Given Data

STEP 2 - Solve

Time Period

Moving from one endpoint to the other is half a full oscillation:

$$t = \frac{T}{2} \implies T = 2t = 2(0.2) = 0.4\text{ s}$$

Frequency

$$f = \frac{1}{T} = \frac{1}{0.4} = 2.5\text{ Hz}$$

Amplitude

The full span between endpoints is $2A$:

$$A = \frac{d}{2} = \frac{0.50}{2} = 0.25\text{ m} = 25\text{ cm}$$

Force Constant

$$T = 2\pi\sqrt{\frac{m}{k}} \implies k = \frac{4\pi^2 m}{T^2}$$

$$k = \frac{4 \times (3.1416)^2 \times 0.25}{(0.4)^2} = \frac{4 \times 9.8696 \times 0.25}{0.16} = \frac{9.8696}{0.16}$$

$$k \approx 61.7\text{ N/m}$$

Summary

Hall Voltage Across the Width of a Copper Slab

STEP 1 - Given Data

STEP 2 - Solve

Hall Voltage Formula

$$V_H = \frac{BI}{net}$$

where $t$ is the dimension of the slab parallel to the magnetic field $B$.

Since $B$ is perpendicular to the plane of the slab (i.e. through the thickness), the relevant dimension in the formula is the thickness $t = 0.5\times10^{-2}\ \text{m}$, and the Hall voltage develops across the width $w$.

Calculation

Numerator: $$B \cdot I = 1.5 \times 50 = 75$$

Denominator: $$n \cdot e \cdot t = (8.4 \times 10^{28})(1.6 \times 10^{-19})(0.5 \times 10^{-2})$$

$$= 8.4 \times 1.6 \times 0.5 \times 10^{28-19-2} = 6.72 \times 10^{7}$$

Hall Voltage: $$V_H = \frac{75}{6.72 \times 10^{7}} = 1.116 \times 10^{-6}\ \text{V}$$

$$\boxed{V_H \approx 1.12\ \mu\text{V}}$$

Result

The magnitude of the Hall voltage across the width of the copper slab is approximately

$$V_H \approx 1.12\ \mu\text{V}$$

This very small value is characteristic of a metal such as copper, where the high free electron concentration produces a very small drift velocity and hence a tiny Hall voltage.

Length of the Unit Cube for Sodium (BCC)

Step 1 - Extract: Given Data

Step 2 - Solve

Atoms per unit cell (BCC): $$n = 8\times\tfrac{1}{8} + 1 = 2$$

Density relation: $$\rho = \frac{nM}{N_a,a^3}\quad\Rightarrow\quad a^3 = \frac{nM}{\rho N_a}$$

Substitute: $$a^3 = \frac{2\times 23}{0.971\times 6.022\times 10^{23}} = \frac{46}{5.847\times 10^{23}}$$

$$a^3 = 7.867\times 10^{-23}\ \text{cm}^3$$

Cube root: $$a = (7.867\times 10^{-23})^{1/3} = (78.67\times 10^{-24})^{1/3}\ \text{cm}$$

$$78.67^{1/3} \approx 4.286,\qquad (10^{-24})^{1/3} = 10^{-8}$$

$$\boxed{a \approx 4.29\times 10^{-8}\ \text{cm} = 4.29\ \text{Å}}$$

Result

The length of the unit cube of sodium is approximately $4.29\ \text{Å};(4.29\times10^{-8}\ \text{cm})$, which agrees well with the accepted experimental value of ~4.28 Å.

Digital Circuit: $y = (C + \bar{B}A)(A + \bar{B} + D)$

Step 1: Extract Given Data

Expression: $$y = (C + \bar{B}A)(A + \bar{B} + D)$$

Inputs: A, B, C, D (4 inputs → $2^4 = 16$ combinations)

Gates required: OR, AND, NOT only.

Step 2: Decompose the Expression

• NOT gate: $\bar{B}$
• AND gate 1: $\bar{B}A$
• OR gate 1 (first factor): $P = C + \bar{B}A$
• OR gate 2 (second factor): $Q = A + \bar{B} + D$
• AND gate 2 (final): $y = P \cdot Q$

Gate count: 1 NOT, 2 AND, 2 OR.

Step 3: Circuit Diagram

 B ---[NOT]---+--------------------> B̄
              |
              |    B̄
              +--->[AND1]---> B̄A ---+
 A -----+--------->              |   |
        |                        C---+->[OR1]---> P = C + B̄A ---+
        |                                                        |
        |                                                     [AND2]---> y
        |    A ----+                                             |
        |          |                                             |
        +----------+                                             |
              B̄  --+--->[OR2]---> Q = A + B̄ + D ----------------+
              D ---+

Gate list:

1. NOT: input B → output $\bar{B}$
2. AND1: inputs $\bar{B}$, A → output $\bar{B}A$
3. OR1: inputs C, $\bar{B}A$ → output $P$
4. OR2 (3-input): inputs A, $\bar{B}$, D → output $Q$
5. AND2: inputs P, Q → output $y$

Step 4: Truth Table

Intermediate columns: $\bar{B}$, $\bar{B}A$, $P = C + \bar{B}A$, $Q = A + \bar{B} + D$, $y = P\cdot Q$

Verification of a few rows:

• Row A=0,B=1,C=1,D=0: $\bar B=0$, $\bar BA=0$, $P=1+0=1$, $Q=0+0+0=0$, $y=1\cdot0=0$ ✓
• Row A=1,B=0,C=0,D=0: $\bar B=1$, $\bar BA=1$, $P=0+1=1$, $Q=1+1+0=1$, $y=1$ ✓
• Row A=0,B=1,C=1,D=1: $P=1$, $Q=0+0+1=1$, $y=1$ ✓

Summary

• Gates used: 1 NOT, 2 AND, 2 OR
• Output $y = 1$ for 9 of the 16 input combinations, namely $ABCD = $ 0010, 0011, 0111, 1000, 1001, 1010, 1011, 1110 and 1111.