Digital Logic · Unit 10
Shift Registers and Data Processing
Exam-focused notes for Shift Registers and Data Processing (Digital Logic, BIT103): what the TU syllabus asks and how it has actually been tested, with 11 solved past questions from this unit.
What this unit covers
- Shift register types and operation
- Serial-in serial-out shift register
- Parallel-in parallel-out shift register
- Shifter circuits
- Parity generator and checker
- Status register and processor registers
- ALU and common bus architecture
Serial-in serial-out shift register
Define shift register. Explain the operation of 4-bit Serial-In Serial-Out Shift register with data input 1011. [1+4]
- Register type: 4-bit Serial-In Serial-Out (SISO) - Number of flip-flops: 4 - Data input: 1011 - Marks distribution: 1 (definition) + 4 (operation) No values missing. The entry convention (MSB-first vs LSB-first) is not specified; I will state the conventi...
Full solved answer →Draw a Serial-In Serial-Out Shift register and explain it. [5]
A Serial-In Serial-Out (SISO) shift register is a sequential logic circuit in which data is entered one bit at a time (serially) from one end and shifted out one bit at a time (serially) from the other end, synchronized by a clock signal. --- More precisely...
Full solved answer →Shifter circuits
Define shifter. Design a 4-bit shifter circuit. [1+4]
--- A shifter is a combinational logic circuit that shifts the bits of a binary input word either to the left or to the right by one or more bit positions. It can also perform logical shift, arithmetic shift, or circular (rotate) operations depending on the...
Full solved answer →Parallel-in parallel-out shift register
Explain the operation of 4-bit Parallel-In parallel-Out Shift register with data input 1010. [5]
- Register type: 4-bit PIPO - Data input to load: $1010$ - Interpreting bits (MSB to LSB): $D3=1,\ D2=0,\ D1=1,\ D0=0$ --- A Parallel-In Parallel-Out (PIPO) shift register loads all data bits at the same time (parallel input) and makes all output bits avail...
Full solved answer →Draw a Parallel-In Parallel-Out Shift register and explain it. [5]
A Parallel-In Parallel-Out (PIPO) shift register is a type of shift register in which all data bits are loaded simultaneously (in parallel) into the register and all bits are also available at the output simultaneously (in parallel). It acts primarily as a ...
Full solved answer →Parity generator and checker
Write short notes on: (Any two) a.) ASCII Code b.)Logic micro operation c.) State table [5]
--- ASCII stands for American Standard Code for Information Interchange. - It is a 7-bit character encoding standard used to represent text in computers and communication devices. - A 7-bit ASCII code can represent 2⁷ = 128 different characters. - These cha...
Full solved answer →Write short notes on: a.) Parity generator b.) State Diagram [2.5+2.5]
Definition: A parity generator is a combinational logic circuit that generates a parity bit (either even or odd) to be appended to a binary data word for the purpose of error detection during data transmission. Working Principle: - The circuit takes n data ...
Full solved answer →Logic Gates Transmission Error Detection
The term LOGIC GATES is to be transmitted as 12 bytes of data. Each character in the term has an ASCII value. The system uses odd parity and the leftmost bit is used as parity bit. An additional parity byte is also sent after the term. The following bytes have arrived at their destination.
| letters | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | |
|---|---|---|---|---|---|---|---|---|---|
| 1 | L | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 |
| 2 | O | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 |
| 3 | G | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 |
| 4 | I | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 |
| 5 | C | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 |
| 6 | ⟨space⟩ | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| 7 | G | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 |
| 8 | A | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 |
| 9 | T | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 |
| 10 | E | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 |
| 11 | S | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 |
| 12 | Parity byte | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 |
a. Locate which character contains an error.
b. Locate the bit that has been transmitted incorrectly.
c. Explain how you have arrived at your conclusion.
[10]
- Message: "LOGIC GATES" transmitted as 12 bytes (11 characters + 1 parity byte). - Odd parity, leftmost bit = parity bit. - Received bit matrix (rows 1-11 = characters, row 12 = parity byte): Row Char b1 b2 b3 b4 b5 b6 b7 b8 -------------------------------...
Full solved answer →Status register and processor registers
Write short notes on: (Any two) a. BCD code b. Status Register c. Ring Counter [5]
--- BCD (Binary Coded Decimal) is a numeric code in which each decimal digit (0-9) is represented individually by its 4-bit binary equivalent. - Uses 4 bits per decimal digit - Only the combinations 0000 to 1001 are valid (representing 0-9) - Combinations 1...
Full solved answer →Explain processor registers and ALU connection through common buses with a suitable diagram. [5]
Inside a processor, registers and the ALU (Arithmetic Logic Unit) must be interconnected so that data can flow between them efficiently. A common bus (or internal bus) is a shared set of wires/lines used to transfer data between multiple registers and the A...
Full solved answer →Shift register types and operation
Define shift register with its types. [5]
A shift register is a sequential logic circuit consisting of a cascade of flip-flops connected in series, where data is stored and shifted (moved) from one flip-flop to the next on each clock pulse. It is used for temporary data storage, data transfer, and ...
Full solved answer →Make Unit 10 stick
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