Input / Output Organization

I/O interface

An I/O interface is the hardware circuit between the CPU buses and an I/O device. It contains registers (data, status and control), an address decoder, and timing and interrupt logic. The CPU reads and writes these registers to control the device.

Functions of an I/O interface

• Device selection: it decodes the address on the address bus and selects the correct device.
• Data buffering: it holds data in a register so that the fast CPU and the slow device can each work at their own speed.
• Data conversion: it changes the format of the data, for example parallel to serial and serial to parallel.
• Signal conversion: it matches the voltage levels and the timing of the device to those of the CPU.
• Control and timing: it gives commands to the device, and makes the read, write and handshake signals in the right order.
• Status reporting: it tells the CPU if the device is ready, busy or in error.
• Interrupt generation: it sends an interrupt request when the device needs service.
• Error detection: it can check for parity or framing errors in the data.

 CPU buses          I/O interface           Device
 Data    <==>   [data buffer      ]  <==>   data
 Address  ==>   [address decoder  ]
 Control <==>   [control / status ]  <==>   signals
 Interrupt <==  [interrupt logic  ]

Why an interface is needed

The CPU and the I/O devices are very different, so a direct connection is not possible.

Devices also differ from each other in the form of data and the operations they accept. Without an interface, the CPU would have to know the details of each device and would waste time waiting for slow ones. An interface gives the CPU one simple and uniform way to deal with every device. It also protects the CPU from the electrical and timing problems of the device.

Peripheral devices are the external devices that are connected to the computer to give it input, take output from it, or store data. They are of three kinds.

• Input devices: keyboard, mouse, scanner, microphone, webcam, joystick, light pen, barcode reader.
• Output devices: monitor, printer, plotter, speakers, projector.
• Storage (secondary) devices: hard disk, SSD, magnetic tape, CD/DVD, pen drive.

Communication devices such as a modem and a network card are also peripherals.

An I/O port is a point of connection, with an address, through which the CPU exchanges data with an external device. A port is usually a register (or a group of registers) in an I/O interface chip. Each port is joined to the device on one side and to the CPU buses on the other.

Functions of I/O ports

• Data exchange: the port holds the data word on its way between the CPU and the device. An input port passes data from a device to the CPU. An output port passes data from the CPU to a device.
• Addressing: each port has a unique address (or port number). The CPU selects a port by this address. Isolated I/O uses the IN and OUT instructions, and memory mapped I/O uses ordinary memory instructions.
• Buffering: the port holds the data until the receiving side is ready. In this way, the fast CPU and the slow device work at their own speeds.
• Control and status: control ports let the CPU command the device, for example to start or stop it. Status ports let the CPU read flags such as ready, busy and error.
• Signal conversion: the port may convert the voltage levels and the form of data, for example between parallel and serial.

Characteristics of ports

• Parallel ports send many bits at the same time on several lines. They are fast over short distances. The printer port is an example.
• Serial ports send one bit at a time on a single line. They need fewer wires and work over longer distances. RS-232, USB and SATA are examples.
• Input, output or bidirectional: a port may work in one direction or in both.
• Width: a port is typically 8, 16 or 32 bits wide.
• Programmable: in chips like the 8255, software decides if a port is input or output and how it works.

  CPU <==== data/address/control buses ====> [Port] <----> Device

Significance

Ports make the CPU independent of the details of the devices. The CPU only reads and writes port registers, and the interface deals with the device. New devices can be attached to a standard port such as USB without changing the CPU. Ports also provide a single controlled point, so that the CPU can check the status and avoid errors during exchange of data. Without ports, there would be no orderly way to join the CPU to the outside world.

Role of peripheral devices

Peripheral devices connect a computer to the outside world. Without them, the CPU and memory could compute but could not receive any data or show any result. They have three roles.

• Input: devices such as the keyboard, mouse and scanner bring data and commands into the computer.
• Output: devices such as the monitor and printer show or print the results for the user.
• Storage: devices such as the hard disk, SSD and tape keep programs and data for a long time, as main memory loses its contents on power off.

Communication devices such as network cards and modems connect the computer to other computers.

Differences from the CPU

Peripherals differ from the CPU in many ways. They are slower, since they often have mechanical parts. They send data in different formats, for example serial bits or analog signals. They use different voltage levels and timing. Each device also works at its own speed. So the CPU cannot be connected to the device directly.

Interaction through the I/O interface and ports

An I/O interface is placed between the device and the CPU buses. It does the following work.

• It decodes the address and selects the right device.
• It holds data in a buffer register, to match the speeds.
• It changes the data format and signal levels.
• It gives status information, such as ready, busy and error, and takes commands.
• It raises interrupts when the device needs attention.

The CPU sees the interface as a few registers, called ports. These are the data port, the status port and the control port.

 CPU <--> System buses <--> [ I/O interface ] <--> Device
                           (data, status, control ports)

To output a character to a printer, the CPU first reads the status port to check that the printer is ready. Then it writes the character to the data port. The interface passes it to the printer with the correct handshake signals. The CPU can then be informed about completion by a status flag or by an interrupt.

To get a key from a keyboard, the key press sets the ready flag in the status port. The CPU reads the data port to get the key code, and this clears the flag.

The ports are addressed either by special IN and OUT instructions (isolated I/O), or by ordinary memory instructions (memory mapped I/O). Larger transfers use DMA, so that the CPU is not involved in every word. In this way the interface and ports let a fast CPU work smoothly with many different and slow devices.

The main functions of an Input/Output unit are:

• Interfacing the CPU and memory with the I/O devices through the system bus.
• Selecting the correct device by decoding the address.
• Converting data between the different formats and signal levels of the device and the CPU (for example parallel and serial).
• Matching the speed of the fast CPU to the slow devices, by buffering data.
• Giving the CPU control and status information, such as ready, busy and error.
• Detecting errors and sending an interrupt when the device needs service.

An I/O interface is the hardware that joins an I/O device to the CPU buses. The CPU is fast and works with parallel words, while a device may be slow, serial and electromechanical. The interface makes the two work together.

 CPU buses                 Interface                Device
+----------+     +-----------------------+     +----------+
| Data bus |<--->| Data register/buffer  |<--->|  data    |
| Address  |---->| Address decoder       |     |          |
| Control  |<--->| Control, status regs  |<--->| control  |
| (RD, WR) |     | Timing and control    |     | and      |
| Interrupt|<----| Interrupt logic       |     | status   |
+----------+     +-----------------------+     +----------+

Components of a typical interface

Address decoder. The interface has one or more addresses. The decoder looks at the address bus and the chip select signal. It enables the interface only when its own address is seen.

Data register (buffer). It holds the data word on its way between the bus and the device. Because of the buffer, the CPU can send data at its own speed and the device can take it at its own speed.

Control register. The CPU writes commands here. A command may start the device, set the mode, choose the direction or enable the interrupt.

Status register. It has flag bits such as ready, busy, overrun and error. The CPU reads them to know the condition of the device.

Timing and control logic. It makes the read, write and handshake signals in the right order for the device, so that data is exchanged safely.

Interrupt logic. When the device is ready or has an error, the logic raises an interrupt request to the CPU.

Operation

For an output, the CPU puts the address of the interface on the address bus and the data on the data bus, and gives a write signal. The interface latches the data in its data register and sends it to the device with the right handshake signals. It then sets a flag to say that the device has the data.

For an input, the device places the data in the data register and sets the ready flag. The CPU reads the status, sees the flag, and reads the data register. This read also clears the flag.

Other tasks

The interface may convert the data from parallel to serial form and back. It may also change the voltage levels, check parity for errors, and decode commands from the CPU.

A programmable interface chip, like the Intel 8255, lets software choose the mode of each port. In this way, one chip can be used with many devices.

Why the design is needed

Without an interface, the CPU would have to know the speed, voltage and timing of every device. With it, the CPU sees each device as a few simple registers, and the interface hides all the other details.

The transfer rate of a tape is the number of bits passing the read head per second. It equals the recording density times the tape speed.

$$\text{Transfer rate} = \text{density} \times \text{speed} = 1600 \times 120$$

$$\text{Transfer rate} = 192{,}000 \text{ bytes per second}$$

The eight tracks are read in parallel, so one bit from each track forms one byte at every position. Therefore the transfer rate is 192,000 bytes per second (about 1.54 million bits per second).

In a computer, the CPU must address both memory locations and I/O device registers. There are two ways to do this.

Isolated I/O keeps a separate address space for I/O. The CPU uses special instructions (IN and OUT) and a control signal such as IO/M to tell whether the address belongs to memory or to an I/O port.

Memory mapped I/O gives the I/O registers addresses from the same space as memory. The CPU uses the ordinary load and store instructions to talk to devices. No separate control signal is needed.

Difference between the two

Advantages of isolated I/O

• The whole memory address space is free for memory.
• I/O instructions stand out clearly in the program, so the code is easy to read.
• Port address decoding is simple because the number of ports is small.

Disadvantages of isolated I/O

• Only a few instructions (IN and OUT) can work with I/O, and they usually move data only through the accumulator.
• Extra control signals and extra instructions make the CPU more complex.
• Arithmetic or logic on device data cannot be done directly.

Advantages of memory mapped I/O

• All memory instructions work on I/O registers, so one can add, compare, shift or test bits of a device register directly.
• No special instructions or control pins are needed, so the CPU design is simpler.
• Many more I/O devices can be addressed.

Disadvantages of memory mapped I/O

• Device addresses take away a part of the memory space. This matters for a small address space.
• Address decoding is more complex, because the full address must be decoded for each device.
• It is harder to spot I/O operations in a program, since they look like normal memory accesses.

Which one to choose

A small processor with a limited address space and few devices often prefers isolated I/O, so that no memory addresses are lost. A modern processor with a large address space (32 or 64 bits) prefers memory mapped I/O, because the lost addresses hardly matter and the programming is far more flexible.

(i) Design of a typical I/O interface

An I/O interface is the hardware between the CPU buses and an I/O device. Devices differ from the CPU in speed, data format and signal levels. The interface hides these differences.

 CPU buses                 Interface                Device
+----------+     +-----------------------+     +----------+
| Data bus |<--->| Data register/buffer  |<--->|  data    |
| Address  |---->| Address decoder       |     |          |
| Control  |<--->| Control, status regs  |<--->| control  |
| (RD, WR) |     | Timing and control    |     | and      |
| Interrupt|<----| Interrupt logic       |     | status   |
+----------+     +-----------------------+     +----------+

The main blocks are these:

• Address decoder: it checks the address on the address bus and selects the interface when its own address is seen.
• Data register (buffer): it holds the word being moved. It lets the fast CPU and the slow device work at different speeds.
• Control register: the CPU writes commands here, such as start, stop or the direction of transfer.
• Status register: it holds flags like ready, busy and error, which the CPU can read.
• Timing and control logic: it makes the read and write signals and the handshake signals for the device.
• Interrupt logic: it raises an interrupt request when the device needs service.

The CPU reads and writes these registers like memory locations (memory mapped) or through IN and OUT instructions (isolated). The interface also converts data between parallel form (CPU) and serial form (some devices) and changes voltage levels where needed.

(ii) Interrupts and how they are handled

An interrupt is a signal that makes the CPU stop the program it is running, serve an urgent event, and then come back. It lets the CPU avoid waiting for slow devices.

When an interrupt request arrives, the CPU does the following.

First, it completes the instruction it is executing. Then it checks whether interrupts are enabled. If they are, it sends an interrupt acknowledge.

Next, it saves the return address (the program counter) and the status flags on the stack. Further interrupts are usually disabled for a moment.

Then it finds the address of the service routine. In a vectored interrupt, the device supplies a vector number that points to the routine. In a non-vectored interrupt, the CPU jumps to one fixed address, and the routine polls the devices to find the source.

The interrupt service routine (ISR) runs next. It serves the device, for example by reading the data register. It ends with a return-from-interrupt instruction.

Finally, the CPU pops the saved flags and the program counter and carries on with the interrupted program as if nothing had happened.

If several devices interrupt together, priority decides which one is served first. Priority can be set by software polling or by hardware such as a daisy chain or a priority encoder.

Serial communication sends the bits of data one after another over a single line. For the receiver to understand the bits, it must know where each bit and character starts and ends. There are two ways to do this.

Synchronous communication

The sender and the receiver work with the same clock. Either the clock is sent on a separate line, or it is recovered from the data signal. Data is sent in large blocks (frames), which start with one or more synchronising characters (SYN) and end with an end marker. There are no start and stop bits for each character. Examples are the HDLC and SDLC protocols, SPI and Ethernet.

Asynchronous communication

The sender and the receiver have no common clock. Each character is sent in its own frame, with a start bit (0) in front and one or two stop bits (1) at the end. A parity bit may be added. The receiver synchronises on the falling edge of each start bit and reads the following bits at the agreed baud rate. Examples are the RS-232 serial port, a UART and a keyboard link.

 Idle  Start  D0 D1 D2 D3 D4 D5 D6 D7  Parity  Stop  Idle
 ‾‾‾‾|_____|   data bits (8)              |‾‾‾‾‾|‾‾‾

For example, to send the character "A" (ASCII 01000001) with one start bit, 8 data bits and one stop bit, the frame is 10 bits long. Only 8 of these carry data.

Differences

In short, synchronous communication is better for fast, steady transfer of large amounts of data, and asynchronous communication is better for slow, irregular transfers such as typing on a keyboard.

In the synchronous serial mode, the sender and receiver share a common clock, and data bits are sent continuously in blocks (frames) without start and stop bits for each character. It is fast, but needs clock or synchronising characters.

In the asynchronous serial mode, there is no common clock. Each character is framed by a start bit and one or two stop bits, so the receiver can synchronise on every character. It is simple and cheap but has extra bits as overhead, so it is slower. A keyboard link is an example.

When two units use their own independent clocks, data moves between them by asynchronous transfer. The sender must show that the data is valid, and the receiver must show that it has taken it. The two methods are strobe control and handshaking.

Strobe control

A single control line, the strobe, tells when to transfer. In source-initiated strobe, the source puts data on the bus and then activates the strobe. The destination latches the data on the strobe. The source then removes the strobe and the data.

In destination-initiated strobe, the destination activates the strobe to ask for data. The source puts data on the bus. The destination latches it and removes the strobe, and the source removes the data.

 Data   ----<====valid====>----
 Strobe ______|‾‾‾‾‾‾‾‾‾|______

The weakness is the lack of acknowledgement. The source does not know that the destination received the data, and the destination does not know that the data is really valid.

Handshaking

Handshaking uses two lines, one in each direction, so that every action gets a reply.

In source-initiated handshaking, the lines are data valid and data accepted. The sequence is:

1. The source puts data on the bus and enables data valid.
2. The destination takes the data and enables data accepted.
3. The source disables data valid and removes the data.
4. The destination disables data accepted. The system is ready for the next word.

In destination-initiated handshaking, the lines are ready for data and data valid. The destination first enables ready for data. The source places data and enables data valid. The destination latches the data and disables ready for data. Finally, the source disables data valid.

Comparison

A time-out circuit is often added with handshaking, to flag an error if a unit does not reply. Handshaking is used in most real interfaces, because it works safely for units of any speed.

In asynchronous data transfer, the source and the destination units have independent clocks. They must therefore use control signals to agree on when data is valid and when it has been taken. Handshaking uses two control lines, one in each direction. In destination-initiated transfer, the destination starts the exchange by saying that it is ready to receive data.

Control lines

• Ready for data: this line goes from the destination to the source. It tells the source that the destination is ready to take a word.
• Data valid: this line goes from the source to the destination. It tells the destination that the data on the bus is valid.

        data bus (8 or 16 lines)
  +--------+ ===================> +-------------+
  | Source |   data valid  ------> | Destination |
  |  unit  | <------ ready for data|    unit     |
  +--------+                       +-------------+

Sequence of events

The destination first activates "ready for data". This shows that it wants a word and has room for it.

When the source sees ready for data, it places the data word on the data bus. After the data has settled, it activates "data valid".

The destination sees data valid and knows that the bus holds a good word. It latches the word into its register.

After latching the data, the destination removes "ready for data". This tells the source that the word has been taken.

The source sees ready for data go low. It removes the data from the bus and also disables "data valid".

The system is now back in the starting state. The destination can raise ready for data again to ask for the next word.

Timing diagram

 Ready for data  __|‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾|________
 Data valid      ______|‾‾‾‾‾‾‾‾‾‾|________
 Data bus        ______<==valid====>________
                  1     2    3     4    5

Here 1 is where the destination asks, 2 is where the source puts data and data valid, 3 is where the destination latches the data, 4 is where ready for data is removed, and 5 is where the source removes data valid and data.

Why this is reliable

Each signal change is a reply to the other unit's signal change. The source does not drop the data until the destination says it has taken it. The destination does not take the data until the source says it is valid. So no word is lost or read twice, whatever the speeds of the two units.

Compared with the source-initiated method

In source-initiated handshaking the source starts with data valid, and the destination answers with data accepted. In the destination-initiated method, the receiver controls the pace. The source cannot send before it is asked. This is useful when the receiver, such as a slow printer, is the one that knows when it can accept data.

Use

Parallel interfaces such as Centronics printer ports, and many bus protocols, use this style of handshake. A time-out circuit can be added to signal an error if the other unit never replies.

When two units such as the CPU and an I/O interface do not share a common clock, they exchange data by asynchronous transfer. The sender must show when the data is valid, and the receiver must show that it has accepted it. For this purpose, two methods are used: strobe control and handshaking.

Method 1: Strobe control

A single control line, called the strobe, times the transfer. It is driven by one of the two units.

Source-initiated strobe. The source puts the data on the bus. After a short delay, it activates the strobe. The destination latches the data on the strobe. Then the source disables the strobe and later removes the data. For example, the CPU writes to a port in this way.

Destination-initiated strobe. The destination activates the strobe to request data. The source puts the data on the bus in reply. The destination latches the data and removes the strobe. The source then removes the data. For example, the CPU reads from a port in this way.

The weak point is that there is no reply. In the source-initiated case, the source cannot know whether the destination took the data. In the destination-initiated case, the destination cannot know whether the source has put valid data.

Source-initiated        Destination-initiated
 Data   =<valid>=        Data   ====<valid>=
 Strobe __|‾‾|___        Strobe __|‾‾‾‾‾|___
 (source -> dest)        (dest -> source)

Method 2: Handshaking

Handshaking adds a second control line so that each unit acknowledges the action of the other. Both signals change in a fixed order, so there is no doubt.

Source-initiated handshaking. Lines are "data valid" (source to destination) and "data accepted" (destination to source). The source puts data on the bus and enables data valid. The destination accepts the data and enables data accepted. The source sees this, disables data valid and removes the data. The destination then disables data accepted.

Destination-initiated handshaking. Lines are "ready for data" (destination to source) and "data valid" (source to destination). The destination enables ready for data. The source puts the data and enables data valid. The destination latches the data and disables ready for data. The source then disables data valid.

Time-out

If one unit fails, the other waits forever. A time-out circuit is added, which sets an error flag when a reply does not arrive within a set time.

Comparison of the methods

In short, strobe is simple but blind, while handshaking is a little more costly but safe for any pair of units. Most practical interfaces use handshaking.

Asynchronous data transfer

In a digital system, two units such as the CPU and an I/O interface often have their own independent clocks. When data is moved between them without a common clock, the transfer is called asynchronous. The sender must tell the receiver when the data is valid, and the receiver must tell the sender that it has taken the data. This is done by extra control signals. The two main methods are strobe control and handshaking.

Strobe control

Here a single control line, the strobe, tells when the data is valid. It can be driven by the source or by the destination.

In source-initiated strobe, the source places the data on the data bus. After a short delay it activates the strobe. The destination uses the strobe to latch the data. The source then removes the strobe and, after a little more time, removes the data.

In destination-initiated strobe, the destination first activates the strobe to ask for data. The source then places data on the bus. The destination latches it and removes the strobe, after which the source removes the data.

Source-initiated strobe
 Data   ----<====valid====>----
 Strobe ______|‾‾‾‾‾‾‾‾‾|______

The drawback is that the source does not know whether the destination really got the data. In the destination-initiated case, the destination does not know whether the source has put valid data. There is no acknowledgement.

Handshaking

Handshaking solves this problem by using two control lines, one in each direction, so each unit knows what the other has done.

In source-initiated handshaking, the source puts data on the bus and activates the line "data valid". The destination sees it, accepts the data, and activates the line "data accepted". The source sees this and removes data valid. Then the destination removes data accepted. The source can now send new data. The sequence is as follows.

1. The source places data on the bus and enables data valid.
2. The destination accepts the data and enables data accepted.
3. The source disables data valid and removes the data.
4. The destination disables data accepted and is ready for the next transfer.

In destination-initiated handshaking, the two lines are "ready for data" (from the destination) and "data valid" (from the source). The destination first activates ready for data. The source then places data and activates data valid. The destination takes the data and removes ready for data. The source then removes data valid, and the next cycle can start.

Comparison

Handshaking is more reliable and is used in most real interfaces. A time-out circuit can be added to detect a unit that never answers.

Concept of an interrupt

An interrupt is a signal that makes the CPU stop its current program for a while, run a special routine called the interrupt service routine (ISR), and then go back to the program. It lets the CPU respond quickly to events such as a key press, a disk finishing, or an error, without wasting time in checking for them again and again.

When the CPU accepts an interrupt, it completes the current instruction. It saves the program counter and the flags on the stack. Then it loads the address of the ISR into the program counter. At the end, a return instruction restores the saved values.

Interrupt hardware

The hardware has the following parts.

• Interrupt request lines: each device has a line (INTR) to the CPU. Many devices can share one line by an OR connection.
• Interrupt flip-flop (mask): it enables or disables interrupts. The CPU can set it by the EI and DI instructions.
• Interrupt controller: a chip such as the Intel 8259 takes requests from many devices, decides the priority, and sends the vector number to the CPU.
• Interrupt acknowledge (INTA): the CPU sends this signal to tell the device that its request is accepted. The device then puts its vector on the data bus.
• Priority circuit: a daisy chain connects the devices in series, so the one nearest to the CPU has the highest priority. A parallel priority encoder can also be used.

Types of interrupts

Hardware interrupts come from outside the CPU. Maskable interrupts (INTR) can be disabled by the program. The non-maskable interrupt (NMI) cannot be disabled and is used for serious events such as a power failure.

Software interrupts are caused by an instruction in a program, such as INT n. They are used to call operating system services.

Exceptions (traps) are raised by the CPU itself when an instruction has a problem, for example a divide by zero, an overflow, an illegal opcode or a page fault.

Interrupts may also be vectored, where the device gives the address of the ISR, or non-vectored, where the CPU jumps to one fixed address and polls the devices to find the cause.

When several interrupts come together, the one with the highest priority is served first. The NMI and exceptions usually come before the ordinary device interrupts.

Definition

An interrupt is a signal sent to the CPU by hardware or software that asks the CPU to stop its current program temporarily and run a special routine, the interrupt service routine (ISR). After the ISR, the CPU returns to the interrupted program from the same place. The CPU saves the program counter and the flags before it jumps, and restores them afterwards.

Interrupts remove the need for the CPU to wait for slow devices. The CPU can do useful work and is called only when something needs attention.

The CPU checks for an interrupt at the end of each instruction cycle. If one is pending and interrupts are enabled, it runs the interrupt cycle.

Types of interrupts

Interrupts are grouped in several ways.

Hardware interrupts come from external devices through the interrupt pins of the CPU.

• Maskable interrupts can be enabled or disabled by the program, using flags such as IF. Keyboard and disk interrupts are examples. The CPU ignores them when they are masked.
• Non-maskable interrupts (NMI) cannot be disabled. They signal very serious events such as power failure or a memory parity error, and have the highest priority.

Software interrupts are caused by an instruction in the program, such as INT n in the 8086 or a system call. They are used by programs to ask the operating system for a service, for example to read a file.

Exceptions (internal interrupts or traps) are raised by the CPU itself when it finds an unusual condition during an instruction. Examples are divide by zero, overflow, an illegal opcode, a page fault and a protection violation. They are synchronous, meaning that they happen at a fixed point of the program.

Interrupts are also classified by the way the service routine is found.

• Vectored interrupts: the device sends a vector number, so the CPU jumps to the correct routine directly. This is fast.
• Non-vectored interrupts: the CPU jumps to one fixed address, and the routine has to poll the devices to find the cause. This is slower.

Priority

When many interrupts come together, priority decides the order. Hardware priority is made by a daisy chain or a priority encoder. Software priority is made by polling. The NMI and the exceptions usually rank above ordinary device interrupts.

Difference between external and internal interrupts

An interrupt is thus the means by which a computer responds quickly to events in the outside world and to errors in the program itself.

A vector interrupt is an interrupt in which the interrupting device itself supplies the address, or a vector number, of its service routine. The CPU uses this vector to look up the starting address of the routine in the interrupt vector table.

So the CPU does not have to poll all devices to find the source. This makes the response fast. For example, in the 8086 each interrupt type number n points to the table entry at address $4n$. Daisy chain priority hardware is often used to send the vector from the highest priority device.

Working of DMA

In Direct Memory Access, an I/O device exchanges a block of data with main memory without the CPU copying each word. The CPU sets up the transfer and then does other work. The steps in the working are as follows.

The CPU writes the starting memory address, the number of words and the direction into the DMA controller. The device then raises a DMA request. The controller sends a bus request to the CPU. The CPU finishes its current cycle, releases the buses and sends a bus grant. The controller puts the address on the address bus and sends the memory and device control signals, and one word moves directly between the device and memory. The controller increases the address and decreases the count. This repeats until the count is zero. At that point the controller returns the bus to the CPU and sends an interrupt to say that the transfer is complete.

The DMA controller

The controller has these main parts:

• Address register: it holds the address of the next memory word.
• Word count register: it holds the number of words still to be moved.
• Control register: it holds the direction and the mode (burst or cycle stealing).
• Data buffer: it connects the controller to the data bus.
• Bus request and bus grant lines: these connect it to the CPU for taking the buses.
• DMA request and acknowledge lines: these connect it to the I/O device.

The CPU can read and write these registers through the register select input, in the same way as for any other interface.

Advantages over other I/O methods

The main advantages of DMA are that it gives the highest data rate, since words are not routed through the CPU, and it frees the CPU for other tasks. It has far less overhead than interrupts because only one interrupt is used for a complete block. Its disadvantages are the extra hardware and the need to share the memory bus, which can slow the CPU a little during the transfer.

Direct Memory Access (DMA) lets an I/O device move data to or from memory without the CPU handling each word. The CPU sets up the transfer in a DMA controller, which then takes over the buses. The controller is given the start address, the word count and the direction. It requests the buses from the CPU, gets a grant, and moves the words one after another. At the end, it interrupts the CPU.

The techniques differ in how the controller shares the bus with the CPU.

Burst (block) transfer

The controller keeps the buses until the whole block is moved. The CPU is blocked from memory during this time. The transfer is very fast, and it suits fast devices like disks. The drawback is that the CPU may have to wait for a long time.

Cycle stealing

The controller takes the bus for a single memory cycle, moves one word, and gives the bus back. This is repeated for each word. The CPU loses only one cycle at a time, so it keeps running, though a little slower. The transfer is slower than burst mode.

Transparent (hidden) DMA

The controller uses the bus only when the CPU does not need it, for example while the CPU is decoding an instruction or working inside the ALU. The CPU is never slowed down. But the speed of the transfer depends on how free the bus is, and the control logic is complicated.

Other arrangements

In a single-operation DMA, one word is transferred per request. In a block DMA, a block is moved for one request, as above. With a daisy chain or a priority circuit, many devices can use one controller, and the highest priority device is served first.

Comparison

Advantages

The CPU is free for other jobs during the transfer. The data rate is high, since each word does not need an instruction. The CPU takes part only at the start and at the end of the block.

DMA is used for disks, network cards, graphics and sound cards, where large blocks must move quickly.

Programmed I/O and interrupt-initiated I/O are two ways in which the CPU controls the transfer of data to and from an I/O device. They differ mostly in how the CPU learns that the device is ready.

Programmed I/O

The CPU runs a program that tests the status flag of the device again and again in a loop. This is called polling. When the flag shows "ready", the CPU transfers one word between the device and a CPU register. Then it goes back to polling for the next word.

The CPU does nothing useful while it waits. It is therefore tied up for the entire time the device takes. The method needs little hardware and is easy to program. It is used when the system has a single job or when the device is very fast.

Interrupt-initiated I/O

Here the CPU starts the device and then goes on with other work. When the device is ready, its interface sends an interrupt request. The CPU completes its current instruction, saves the return address and the flags, and jumps to the interrupt service routine. The routine moves one word, and the CPU returns to the interrupted program.

The CPU is not kept waiting, so it is used well when devices are slow. The cost is the time spent in saving and restoring the state for each interrupt, and the extra hardware for interrupt handling and priority.

Differences

Summary

Programmed I/O is simple but wasteful, because the CPU stays in a loop. Interrupt-initiated I/O uses the CPU much better because the device calls the CPU when needed. Neither is suited to moving big blocks of data at high speed. For that, DMA is used, since in both of these methods the CPU must handle every word.

Modes of data transfer

There are three modes of data transfer between the CPU, memory and I/O devices.

Programmed I/O. The CPU runs a program that polls the status flag of the device. When the device is ready, the CPU moves one word. The CPU is busy waiting for the whole time, which wastes its power.

Interrupt-initiated I/O. The device interrupts the CPU when it is ready. The CPU saves its state, runs the service routine to move a word, and returns. The CPU is free between interrupts, but each word costs the time of an interrupt.

Direct memory access (DMA). A DMA controller moves a whole block between the device and memory, without involving the CPU in each word.

Direct memory access in detail

The CPU first loads the DMA controller with the starting memory address, the word count and the direction of the transfer, and then goes on with its work.

When the device is ready, it sends a DMA request to the controller. The controller sends a bus request to the CPU. The CPU completes the present cycle, puts its buses in the high impedance state, and sends back a bus grant. The controller now controls the buses. It places the memory address on the address bus, activates the read or write signal, and the word passes between the device and memory.

After each word, the address register increases by one and the word count decreases by one. The cycle is repeated until the count is zero. The controller then removes the bus request and interrupts the CPU to say that the block is finished.

DMA can work in burst mode, where the whole block is moved at one go. It can also work in cycle stealing mode, where one word is moved and the bus is given back to the CPU each time.

Why DMA is better than the other modes

In programmed I/O the CPU is occupied by waiting. In interrupt-initiated I/O the CPU is not waiting, but it spends time saving and restoring state for each word, and the rate of transfer is limited by this. In DMA, the data goes straight to memory at the speed of the device and memory. The CPU only sets up the transfer and handles one interrupt at the end. Therefore DMA is the best choice for large blocks of data, and it gives the best use of the CPU. Its only costs are the extra hardware of the controller and some bus sharing.

The DMA controller gets priority over the CPU for the memory bus because an I/O device cannot wait. A device such as a disk delivers data at a fixed speed. If its word is not moved at once, the next word overwrites it and data is lost.

The CPU, on the other hand, can be delayed for a cycle without any harm. It only runs a little slower. Hence the memory cycle goes to the DMA controller first, which also keeps the high speed device working at full rate.

A DMA controller is a hardware unit that lets I/O devices transfer data to or from memory directly, without the CPU moving each word. It takes control of the system buses from the CPU for the time of the transfer.

Schematic of the DMA controller

The controller has an address register for the memory address, a word count register for the number of words, and a control register for the direction and mode. It has a data buffer to connect to the data bus. It also has the lines DMA request and DMA acknowledge to the device, and bus request and bus grant to the CPU. A register select input lets the CPU read and write its registers.

Working of the transfer

The CPU first programs the controller with the starting address, the word count and the direction. The device then raises a DMA request. The controller asks the CPU for the bus. The CPU finishes the present bus cycle and grants the bus. The controller puts the address on the address bus, sends the read or write signals, and the word moves between the device and memory. The address is incremented and the count is decremented. When the count is zero, the controller releases the bus and interrupts the CPU.

Modes of data transfer in DMA

Burst mode (block mode). The controller keeps the bus until the whole block is transferred. The transfer is very fast. But the CPU cannot use the bus for the whole time and may be idle for long. This suits high speed devices such as disks.

Cycle stealing mode. The controller takes the bus for one word, then releases it. The CPU gets the bus in between. The transfer is slower, but the CPU is delayed only by one cycle for each word. This suits slow or medium speed devices.

Transparent mode (hidden mode). The controller uses the bus only in those cycles when the CPU is not using it, for example while the CPU is decoding an instruction. The CPU is never slowed. But the transfer can be delayed, and the circuit is more complex.

Direction of transfer

In a DMA read, data goes from memory to the device. In a DMA write, data goes from the device to memory. A third form, memory to memory transfer, is possible in some controllers.

Comparison of the modes

Advantages

The main gains of DMA are higher speed and a free CPU. The cost is the extra hardware and the need to share the bus.

Cycle stealing is a DMA mode in which the DMA controller takes control of the memory bus for just one memory cycle at a time to move one word. It then gives the bus back to the CPU.

The controller "steals" a cycle from the CPU, so the CPU is delayed by only one cycle per word. The CPU and the DMA transfer therefore share the bus alternately. The transfer is slower than burst mode, but the CPU is never blocked for long. This suits slow or medium speed devices.

A DMA controller is the hardware unit that transfers data between an I/O device and main memory without the CPU, by taking over the system buses. A typical controller (such as the Intel 8237) has the following block structure.

Main blocks

• Address register: it holds the memory address of the word to be moved. It is incremented after each transfer.
• Word count register: it holds the number of words left. It is decremented after each transfer. When it reaches zero, the transfer is over.
• Control register: it holds the mode and the direction of transfer (read from memory or write to memory), and the transfer type such as burst or cycle stealing.
• Data buffer (data bus buffer): it holds the word for a moment and connects the controller to the data bus.
• Address and control logic: it drives the memory read and write lines, and the address bus when the controller is the bus master.
• Status register: it records when the count has reached zero and which channel was served.
• DMA select and register select: these inputs let the CPU address the controller itself, when the CPU programs its registers.

Signals with the CPU and the device

The DMA request line (DRQ) comes from the device and tells the controller that the device wants a transfer. The controller sends a bus request (HOLD) to the CPU. The CPU answers with a bus grant (HLDA) after finishing the present bus cycle. The controller then sends a DMA acknowledge (DACK) to the device. After the block is done, the controller sends an interrupt to the CPU.

Working

When the CPU is the bus master, the controller acts like an I/O interface. The CPU programs it by writing the start address, word count and mode into the registers. The control signals of the CPU (read and write) select the register through the register select input.

Once programmed, the controller waits for DRQ. On DRQ it asks for the bus. When the bus is granted, it places its address register on the address bus and issues the memory and I/O control signals together. The word goes straight from the device to memory or from memory to the device, over the data bus, without entering the CPU.

Then the address register goes up by one and the word count goes down by one. If the count is not zero and the device still requests, the cycle repeats. When the count is zero, the controller gives the bus back and raises an interrupt.

A controller with several channels can serve several devices. Each channel has its own address and count registers. A priority circuit decides which channel is served first when two request at the same time.

Why it is useful

The CPU is involved only at the start and the end of a block. High speed devices like disks can therefore move data at nearly the full memory speed.

Data transfer between the CPU, memory and I/O devices is done in three modes. They differ in how much work the CPU does and how fast the transfer is.

Programmed I/O

The CPU controls the whole transfer by a program. It checks the status flag of the device in a loop. When the flag shows ready, the CPU reads or writes the data register. After that it goes back to checking.

This is simple and needs little hardware. But the CPU is kept busy waiting. This is called busy waiting, and it wastes CPU time, especially when the device is slow.

Interrupt-initiated I/O

Here the CPU does not wait. The device sends an interrupt signal when it is ready. The CPU stops its program, saves its state, and runs the service routine that moves the data. Then it returns to the old program.

The CPU can therefore run other programs while the device is busy. The overhead is the time to save and restore the state for every word. So this mode is good for slow or medium speed devices such as keyboards, but not for large blocks of data.

Direct Memory Access (DMA)

The DMA controller moves blocks of data between the device and memory by itself. The CPU only sets up the start address and word count, and the controller interrupts the CPU at the end. Data goes straight over the system bus, so the CPU is free during the transfer.

DMA is the fastest mode and is used for disks, tapes and network cards. It needs extra hardware, and the controller and the CPU compete for the memory bus.

Comparison

A simple illustration

Think of a student waiting for a parcel. In programmed I/O, the student stands at the gate and keeps looking out. In interrupt-initiated I/O, the student studies and goes to the gate only when the doorbell rings. In DMA, a helper collects all the parcels and places them in the room, and tells the student only when the last one is in.

Choosing a mode

If the device is slow and the system is simple, programmed I/O is enough. If the CPU has other jobs to do, interrupts are better. If large amounts of data must move quickly, DMA is the best choice.

An I/O control method is the way the CPU manages data transfer between itself and an input/output device. It decides who starts the transfer and who moves the data.

There are three main methods:

• Programmed I/O: the CPU runs a program that checks the device status again and again and moves each word itself.
• Interrupt-initiated I/O: the device sends an interrupt signal when it is ready, so the CPU can do other work meanwhile.
• Direct Memory Access (DMA): a DMA controller moves blocks of data between the device and memory without the CPU handling each word.

Direct Memory Access (DMA) is a method in which an I/O device transfers a block of data directly to or from main memory without passing each word through the CPU. A special hardware unit called the DMA controller takes charge of the memory buses for the duration of the transfer. This is much faster than programmed or interrupt-driven I/O, because the CPU does not execute instructions for every word.

How the DMA controller is organised

The controller has an address register, a word count register, a control register and a data buffer. It also has request and grant lines to the CPU and the device.

The address register holds the memory location of the next word. The word count register holds the number of words still to move. The control register holds the direction (read or write) and the mode of transfer.

How a transfer takes place

First, the CPU initialises the controller. It writes the starting memory address into the address register, the number of words into the word count register, and the direction into the control register. After this the CPU carries on with other work.

When the device is ready, it raises a DMA request to the controller. The controller then sends a bus request (HOLD) to the CPU. The CPU finishes its current bus cycle, floats its address, data and control buses to the high impedance state, and replies with a bus grant (HLDA).

Now the controller owns the buses. It puts the address from its address register on the address bus. It then activates the memory read or write signal and the DMA acknowledge to the device. The word moves directly between the device and memory.

After each word the controller increments the address register and decrements the word count register. This repeats until the count becomes zero.

When the count reaches zero, the controller releases the buses by removing the bus request. It also sends an interrupt to the CPU to say that the whole block has been transferred. The CPU then resumes normal control of the buses.

Modes of DMA transfer

In burst (block) mode, the controller keeps the bus until the whole block is moved. In cycle stealing mode, it takes the bus for one word at a time and gives it back, so the CPU is slowed only slightly. In transparent mode, it uses the bus only when the CPU is not using it.

Advantages

DMA gives a high transfer rate and frees the CPU from word-by-word work. It is the best method for fast devices like disks. Its cost is the extra hardware of the controller.

A small example

Suppose a disk must write 512 words into memory starting at address 2000. The CPU loads 2000 into the address register and 512 into the word count register, sets the direction to "write to memory", and starts the controller. The CPU then runs another program. The controller moves all 512 words, one after another, and finally interrupts the CPU. The CPU spent time only on the set-up and on the final interrupt, not on 512 separate transfers.

(a) Communication of the buses with memory and I/O

A computer has three buses: the address bus, the data bus and the control bus. The CPU uses them to talk to both memory and I/O devices. There are two ways to connect I/O devices to the buses.

In the first way, there is one common set of buses for both memory and I/O, with separate read and write lines for I/O. This is isolated I/O. The CPU puts an address on the address bus. A control signal tells whether this address is for memory or for an I/O port. Memory and the interfaces both listen to the address, but only the selected one answers.

In the second way, memory and I/O share the same address space and the same read and write lines. This is memory mapped I/O. An address decoder decides whether the address belongs to memory or to an I/O register.

In both cases, the CPU does the following for a write. It places the address on the address bus and the data on the data bus. Then it activates the write signal on the control bus. The selected memory cell or I/O register latches the data. In a read, the selected unit puts its data on the data bus after the read signal.

Each I/O interface has an address decoder, data and control registers, and logic that connects it to the buses. In this way, the same buses serve both memory and I/O.

(b) CPU and IOP communication

An Input Output Processor (IOP) is a small processor with its own instruction set, made only for I/O work. It takes over the I/O job from the CPU and communicates with the memory by DMA.

        +-----+      +--------+
        | CPU |      | Memory |
        +--+--+      +---+----+
           |             |
  ==========+=============+=========== Memory bus
                 |
             +---+---+
             |  IOP  |
             +---+---+
   ====+=======+=======+=======+==== I/O bus
       |       |       |       |
    +--+--+ +--+--+ +--+--+ +--+--+
    | PD1 | | PD2 | | PD3 | | PD4 |
    +-----+ +-----+ +-----+ +-----+

The CPU does not start the I/O itself. The sequence is as follows.

The CPU first sends an instruction to the IOP to test the status of the IOP. If the IOP is free, the CPU sends a start instruction. This instruction tells the IOP where the I/O program is in memory.

The IOP then fetches its own program (made of commands that say which device, which operation, how many words and where in memory). It runs these commands, and moves data between the devices and memory by cycle stealing.

When the IOP finishes, it sends an interrupt to the CPU. The CPU then reads the status word of the IOP, which tells whether the operation was completed without error. Based on this, the CPU decides what to do next.

The CPU is free for the full time between starting the IOP and receiving the interrupt, so it can work on other programs. This arrangement is used in large mainframes, where many fast devices are active together.