Draw and explain the block diagram of typical DMA controller.

Main blocks

• Address register: it holds the memory address of the word to be moved. It is incremented after each transfer.
• Word count register: it holds the number of words left. It is decremented after each transfer. When it reaches zero, the transfer is over.
• Control register: it holds the mode and the direction of transfer (read from memory or write to memory), and the transfer type such as burst or cycle stealing.
• Data buffer (data bus buffer): it holds the word for a moment and connects the controller to the data bus.
• Address and control logic: it drives the memory read and write lines, and the address bus when the controller is the bus master.
• Status register: it records when the count has reached zero and which channel was served.
• DMA select and register select: these inputs let the CPU address the controller itself, when the CPU programs its registers.

Signals with the CPU and the device

The DMA request line (DRQ) comes from the device and tells the controller that the device wants a transfer. The controller sends a bus request (HOLD) to the CPU. The CPU answers with a bus grant (HLDA) after finishing the present bus cycle. The controller then sends a DMA acknowledge (DACK) to the device. After the block is done, the controller sends an interrupt to the CPU.

Working

When the CPU is the bus master, the controller acts like an I/O interface. The CPU programs it by writing the start address, word count and mode into the registers. The control signals of the CPU (read and write) select the register through the register select input.

Once programmed, the controller waits for DRQ. On DRQ it asks for the bus. When the bus is granted, it places its address register on the address bus and issues the memory and I/O control signals together. The word goes straight from the device to memory or from memory to the device, over the data bus, without entering the CPU.

Then the address register goes up by one and the word count goes down by one. If the count is not zero and the device still requests, the cycle repeats. When the count is zero, the controller gives the bus back and raises an interrupt.

A controller with several channels can serve several devices. Each channel has its own address and count registers. A priority circuit decides which channel is served first when two request at the same time.

Why it is useful

The CPU is involved only at the start and the end of a block. High speed devices like disks can therefore move data at nearly the full memory speed.