Discuss the design of a typical input or output interface.
Discuss the design of a typical input or output interface.
Quick answer
An I/O interface is the hardware that joins an I/O device to the CPU buses. The CPU is fast and works with parallel words, while a device may be slow, serial and electromechanical. The interface makes the two work together.
CPU buses Interface Device
+----------+ +-----------------------+ +----------+
| Data bus |<--->| Data register/buffer |<--->| data |
| Address |---->| Address decoder | | |
| Control |<--->| Control, status regs |<--->| control |
| (RD, WR) | | Timing and control | | and |
| Interrupt|<----| Interrupt logic | | status |
+----------+ +-----------------------+ +----------+
Components of a typical interface
Address decoder. The interface has one or more addresses. The decoder looks at the address bus and the chip select signal. It enables the interface only when its own address is seen.
Data register (buffer). It holds the data word on its way between the bus and the device. Because of the buffer, the CPU can send data at its own speed and the device can take it at its own speed.
Control register. The CPU writes commands here. A command may start the device, set the mode, choose the direction or enable the interrupt.
Status register. It has flag bits such as ready, busy, overrun and error. The CPU reads them to know the condition of the device.
Timing and control logic. It makes the read, write and handshake signals in the right order for the device, so that data is exchanged safely.
Interrupt logic. When the device is ready or has an error, the logic raises an interrupt request to the CPU.
Operation
For an output, the CPU puts the address of the interface on the address bus and the data on the data bus, and gives a write signal. The interface latches the data in its data register and sends it to the device with the right handshake signals. It then sets a flag to say that the device has the data.
For an input, the device places the data in the data register and sets the ready flag. The CPU reads the status, sees the flag, and reads the data register. This read also clears the flag.
Other tasks
The interface may convert the data from parallel to serial form and back. It may also change the voltage levels, check parity for errors, and decode commands from the CPU.
A programmable interface chip, like the Intel 8255, lets software choose the mode of each port. In this way, one chip can be used with many devices.
Why the design is needed
Without an interface, the CPU would have to know the speed, voltage and timing of every device. With it, the CPU sees each device as a few simple registers, and the interface hides all the other details.
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