Explain how the computer buses can be used to communicate with memory and I/O. Also draw the block diagram for CPU-IOP communication.

(a) Communication of the buses with memory and I/O

In the first way, there is one common set of buses for both memory and I/O, with separate read and write lines for I/O. This is isolated I/O. The CPU puts an address on the address bus. A control signal tells whether this address is for memory or for an I/O port. Memory and the interfaces both listen to the address, but only the selected one answers.

In the second way, memory and I/O share the same address space and the same read and write lines. This is memory mapped I/O. An address decoder decides whether the address belongs to memory or to an I/O register.

In both cases, the CPU does the following for a write. It places the address on the address bus and the data on the data bus. Then it activates the write signal on the control bus. The selected memory cell or I/O register latches the data. In a read, the selected unit puts its data on the data bus after the read signal.

Each I/O interface has an address decoder, data and control registers, and logic that connects it to the buses. In this way, the same buses serve both memory and I/O.

(b) CPU and IOP communication

An Input Output Processor (IOP) is a small processor with its own instruction set, made only for I/O work. It takes over the I/O job from the CPU and communicates with the memory by DMA.

        +-----+      +--------+
        | CPU |      | Memory |
        +--+--+      +---+----+
           |             |
  ==========+=============+=========== Memory bus
                 |
             +---+---+
             |  IOP  |
             +---+---+
   ====+=======+=======+=======+==== I/O bus
       |       |       |       |
    +--+--+ +--+--+ +--+--+ +--+--+
    | PD1 | | PD2 | | PD3 | | PD4 |
    +-----+ +-----+ +-----+ +-----+

The CPU does not start the I/O itself. The sequence is as follows.

The CPU first sends an instruction to the IOP to test the status of the IOP. If the IOP is free, the CPU sends a start instruction. This instruction tells the IOP where the I/O program is in memory.

The IOP then fetches its own program (made of commands that say which device, which operation, how many words and where in memory). It runs these commands, and moves data between the devices and memory by cycle stealing.

When the IOP finishes, it sends an interrupt to the CPU. The CPU then reads the status word of the IOP, which tells whether the operation was completed without error. Based on this, the CPU decides what to do next.

The CPU is free for the full time between starting the IOP and receiving the interrupt, so it can work on other programs. This arrangement is used in large mainframes, where many fast devices are active together.