Block Diagram of 80286 and Its Functional Units

Introduction

The Intel 80286 is a 16-bit microprocessor that is an enhanced version of the 8086. It operates at higher speeds and supports protected mode operation with memory management and protection features. The 80286 is internally divided into four independent functional units that operate in a pipelined fashion to improve overall performance.

Block Diagram of 80286

         +------------------+        +----------------------+
         |   ADDRESS UNIT   |        |    BUS UNIT (BU)     |
         |      (AU)        |        |                      |
         | - Segment Regs   |<------>| - Address Drivers    |
         | - Adder          |        | - Prefetch Queue     |
         | - Descriptor     |        |   (6-byte)           |
         |   Registers      |        | - Bus Control Logic  |
         | - Limit Checker  |        |                      |
         +--------+---------+        +----------+-----------+
                  |                             |
                  |     INTERNAL BUS            |
         +--------+---------+        +----------+-----------+
         | INSTRUCTION UNIT |        |  EXECUTION UNIT (EU) |
         |      (IU)        |        |                      |
         | - Instruction    |<------>| - ALU                |
         |   Prefetch Queue |        | - Register File      |
         | - Instruction    |        | - Barrel Shifter     |
         |   Decoder        |        | - Multiply/Divide    |
         | - Decoded Queue  |        | - Control Logic      |
         +------------------+        +----------------------+
                  |                             |
                  +----------+-----------------+
                             |
                    INTERNAL CONTROL BUS
                             |
              +--------------+--------------+
              |                             |
     EXTERNAL ADDRESS BUS (24-bit)   EXTERNAL DATA BUS (16-bit)

Functional Units of 80286

The 80286 is divided into four major functional units:

1. Bus Unit (BU)

The Bus Unit is responsible for all external bus operations. It acts as the interface between the processor and the external memory or I/O devices.

Functions:

• Fetches instruction bytes from external memory and places them into the 6-byte prefetch queue
• Manages the 24-bit external address bus and 16-bit external data bus
• Controls bus timing, bus cycles, and bus arbitration
• Performs read and write operations to memory and I/O ports
• Contains address drivers and bus control logic

The BU operates independently, so while the Execution Unit is processing one instruction, the BU can simultaneously fetch the next instruction (pipelining).

2. Instruction Unit (IU)

The Instruction Unit is responsible for decoding instructions fetched by the Bus Unit.

Functions:

• Receives raw instruction bytes from the BU's prefetch queue
• Decodes the instructions into a form that the Execution Unit can process
• Maintains a decoded instruction queue (holds up to 3 decoded instructions)
• Uses a predecode stage to identify instruction boundaries and lengths
• Feeds decoded instructions to the Execution Unit in order

The IU works ahead of the EU, so the EU rarely has to wait for instruction decoding, improving throughput.

3. Execution Unit (EU)

The Execution Unit is responsible for actually executing the decoded instructions.

Functions:

• Contains the 16-bit ALU (Arithmetic and Logic Unit) for arithmetic and logical operations
• Contains the Register File (AX, BX, CX, DX, SP, BP, SI, DI, IP, FLAGS)
• Contains a Barrel Shifter for fast shift and rotate operations
• Contains Multiply/Divide hardware for multiplication and division operations
• Receives decoded instructions from the IU and executes them
• Sends memory addresses to the Address Unit when memory access is needed
• Manages the control logic for instruction execution flow

4. Address Unit (AU)

The Address Unit is responsible for memory address calculation and memory protection in both real mode and protected mode.

Functions:

• Contains Segment Registers and Descriptor Registers for memory segmentation
• Performs address calculation using a dedicated adder (segment base + offset)
• Checks limit and attribute of memory segments using the Limit Checker and Attribute PLA (Programmable Logic Array)
• Enforces memory protection in protected mode by verifying access rights
• Generates the final 24-bit physical address sent to the Bus Unit
• Supports a descriptor cache to hold recently used segment descriptors for fast access

The AU is the key unit that enables the 80286's protected mode, allowing it to address up to 16 MB of physical memory and 1 GB of virtual memory.

Summary Table

Conclusion

The 80286 achieves high performance through pipelining of its four functional units. While the EU executes one instruction, the IU decodes the next, and the BU fetches the one after that, all simultaneously. The AU provides the memory management and protection features that distinguish the 80286 from its predecessor, the 8086.

Assembly Language Program to Find the Smallest Number in an Array (8-bit Microprocessor - 8085)

Problem Understanding

• We need to find the smallest (minimum) number in an array of 8-bit data.
• Array size: minimum 15 elements
• We assume:
  • Memory location 2200H stores the length of the array (count = 15 = 0FH)
  • Memory locations 2201H onwards store the array elements
  • Result (smallest number) is stored at memory location 2300H

Assumed Array Data

Expected smallest value = 03H (at address 2204H)

Algorithm / Logic

Step 1: Load the count (length) of array from memory 2200H into register C
Step 2: Point HL register pair to the first element (2201H)
Step 3: Load the first element into Accumulator as the assumed minimum
Step 4: Decrement counter C by 1 (first element already loaded)
Step 5: Advance HL pointer to next element
Step 6: Compare current element (M) with Accumulator (current minimum)
        - If current element >= Accumulator, skip (no update)
        - If current element < Accumulator, update Accumulator with current element
Step 7: Decrement counter C, advance pointer
Step 8: Repeat Steps 6-7 until counter C = 0
Step 9: Store the result (Accumulator) at 2300H
Step 10: HLT

Assembly Language Program (8085 ALP)

; ============================================================
; Program  : Find Smallest Number in an Array
; Array    : Starts at 2201H, Length stored at 2200H
; Result   : Stored at 2300H
; Array Size: 15 elements (0FH)
; ============================================================

        LDA  2200H      ; Load the count (length = 0FH) into Accumulator
        MOV  C, A       ; Move count into register C (loop counter)

        LXI  H, 2201H   ; Point HL pair to the first element of array

        MOV  A, M       ; Load first element into Accumulator
                        ; Assume first element as the current minimum

        DCR  C          ; Decrement counter (first element already read)
        INX  H          ; Advance HL pointer to next element

LOOP:   MOV  B, M       ; Load next array element into register B

        CMP  B          ; Compare Accumulator (current min) with B
                        ; CMP performs A - B and sets flags
                        ; If A <= B, Carry flag = 0, so A is still smaller
                        ; If A > B,  Carry flag = 1, so B is the new minimum

        JC   UPDATE     ; Jump to UPDATE if Carry = 1 (i.e., A > B, B is smaller)
        JZ   SKIP       ; Jump to SKIP if Zero = 1  (i.e., A = B, no update needed)
        JMP  SKIP       ; Jump to SKIP if A < B (A is already smaller)

UPDATE: MOV  A, B       ; Update Accumulator with the new smaller value (B)

SKIP:   INX  H          ; Advance HL pointer to next memory location
        DCR  C          ; Decrement loop counter
        JNZ  LOOP       ; If counter not zero, repeat loop

        STA  2300H      ; Store the smallest number into memory location 2300H

        HLT             ; Stop the program

Step-by-Step Instruction Explanation

Dry Run (Partial Trace)

After the fourteenth comparison the counter in C reaches zero, the loop ends, and STA 2300H stores the accumulator.

Result: memory location 2300H holds 03H, the smallest number in the array, which matches the expected value identified with the assumed data.

Conclusion

The program treats the first element as the assumed minimum and then walks the array once with the HL pair, comparing each element against the accumulator and replacing it whenever a smaller value is found. Since every element is examined exactly once, the routine needs (n - 1) comparisons for n elements, which is 14 comparisons for the 15-element array assumed here, and it works unchanged for any array length placed in 2200H.

System Bus

Definition

A system bus is a group of conducting wires (electrical pathways) that connects the CPU, memory, and input/output devices, allowing them to communicate and transfer information with each other. All peripherals are connected to the microprocessor through the bus.

Bus is a group of conducting wires which carries information, and all the peripherals are connected to the microprocessor through the bus.

Types of System Bus

There are three types of system buses:

1. Address Bus

• A group of conducting wires that carries address information only.
• It is a unidirectional bus, meaning data flows in one direction only - from the microprocessor to memory or from the microprocessor to Input/Output devices.
• The length of the address bus determines the amount of memory a system can address.
  • For example, the 8085 microprocessor has a 16-bit address bus, which means it can address 2^16 = 65,536 (64KB) memory locations.
• The length of the address bus varies with the type of microprocessor.

2. Data Bus

• A group of conducting wires that carries data to and from memory and I/O devices.
• It is a bidirectional bus, meaning data can flow in both directions (from CPU to memory and from memory to CPU).
• The width of the data bus is equal to the word length of the processor.
  • For example, the 8085 microprocessor has an 8-bit data bus.
• A wider data bus allows more data to be transferred at once, improving system performance.

3. Control Bus

• A group of conducting wires that carries control signals from the CPU to memory and I/O devices.
• It coordinates and controls the operations of the system components.
• It carries signals such as:
  • Read/Write signals - to indicate whether data is being read from or written to memory
  • Interrupt signals - to handle interrupt requests
  • Clock signals - to synchronize operations
• It can be both unidirectional and bidirectional depending on the specific control line.

Summary Table

Bus Organization Diagram (8085)

        +------------------+
        |   Microprocessor |
        |     (8085)       |
        +------------------+
              |    |    |
    Address   | Data| Control
      Bus     | Bus |  Bus
    (16-bit)  |(8-bit)| 
              |    |    |
        +-----+----+----+-----+
        |                     |
     Memory               I/O Devices
     (RAM/ROM)

The three buses together form the system bus, which is the backbone of communication in a microprocessor-based system.

Instruction Set and Types of Instructions in 8085 Microprocessor

Definition of Instruction Set

An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions that a microprocessor supports is called the Instruction Set.

• The 8085 microprocessor supports 246 instructions.
• Each instruction is represented by an 8-bit binary value called the Op-code or Instruction Byte.

Types (Kinds) of Instructions in 8085 Microprocessor

The instructions of the 8085 microprocessor are classified into the following categories:

1. Data Transfer Instructions

These instructions move data between registers, memory, and I/O ports without modifying the data.

2. Arithmetic Instructions

These instructions perform arithmetic operations such as addition and subtraction.

3. Logical Instructions

These instructions perform logical (Boolean) operations on data.

4. Branch / Jump Instructions

These instructions alter the normal sequential flow of a program by jumping to a specific address, either conditionally or unconditionally.

5. Stack and Machine Control Instructions

These instructions control the stack operations and the overall machine state.

6. Rotate Instructions

These instructions rotate the bits of the accumulator left or right.

Summary Table

The 8085 instruction set provides a complete set of operations allowing the microprocessor to perform arithmetic, logical, data movement, and program control tasks efficiently.