Instruction Cycle and Timing Diagram of MOV A, B

1. Instruction Cycle (Definition and Structure)

Instruction Cycle is defined as the total time required to fetch and execute an entire instruction.

From the notes:

"The time required to execute and fetch an entire instruction is called instruction cycle."

The instruction cycle is given by:

$$IC = FC + EC$$

Where:

• FC = Fetch Cycle time
• EC = Execute (Execution) Cycle time

Components of Instruction Cycle

Key Terms

• Machine Cycle: The time required by the microprocessor to complete one operation of accessing memory or I/O device. Consists of 3 to 6 T-states.
• T-State: One time period (clock period) of the microprocessor frequency. It is measured from the falling edge of one clock pulse to the falling edge of the next clock pulse.
• The 8085 microprocessor consists of 1 to 6 machine cycles per instruction.

2. Timing Diagram of MOV A, B

Assumptions

1. Microprocessor used: Intel 8085
2. Clock frequency: f (each T-state = 1 clock period = 1/f seconds)
3. The instruction MOV A, B copies the content of register B into register A.
4. Opcode of MOV A, B = 78H (1 byte instruction)
5. The instruction is stored at memory address 2050H (assumption)
6. Since MOV A, B is a register-to-register operation, it requires:
   • 1 Machine Cycle (Opcode Fetch / M1) = 4 T-states
   • No memory read/write is needed in execution (register operation is internal)
   • Total T-states = 4

Machine Cycle Details

Note: For MOV A, B, the execution (moving data from B to A) happens internally during T4 of the opcode fetch cycle itself. No separate execution machine cycle is needed.

Timing Diagram

Clock:
       ___     ___     ___     ___
      |   |   |   |   |   |   |   |
______|   |___|   |___|   |___|   |______
      T1      T2      T3      T4

       |<----------  M1 (Opcode Fetch) ---------->|

ALE:
      ___
     |   |
_____|   |_________________________________________
      T1
      (Address Latch Enable -- high during T1)

Address Bus (A15-A8) / AD7-AD0:
      |--2050H--|
      <valid>   |
      T1        |
                (address lines go high-Z / data phase)

AD7-AD0 (Data Bus -- lower 8 bits multiplexed):
               |--- 78H (Opcode) ---|
               T2        T3
               (Data valid on bus)

RD (Memory Read) -- Active LOW:
              ____________________
_____________|                    |_______________
      T1     T2         T3        T4
             (RD goes LOW -- memory read active)
             (RD goes HIGH after T3)

IO/M (LOW = Memory operation):
_____________________________________________
(stays LOW throughout M1 -- memory operation)

S1, S0 (Status signals for Opcode Fetch = 1,0):
      <S1=1, S0=0 during M1>

Internal Operation (T4):
      Content of Register B is transferred to Register A
      (No external bus activity)

Detailed Description of Each T-State

Summary

Instruction : MOV A, B
Opcode      : 78H  (1 byte)
Machine Cycles : 1 (Opcode Fetch)
T-States    : 4
Operation   : (A) <-- (B)

The timing diagram shows that MOV A, B completes in 4 T-states within a single machine cycle (M1). Since both source (B) and destination (A) are internal CPU registers, no additional memory access machine cycle is required, making it one of the fastest instructions in the 8085 instruction set.

Assembly Language Program to Find the Largest Number in an Array (8085 Microprocessor)

Given Data (Extracted)

The question specifies no fixed numeric values, so standard exam assumptions are made:

Sample Array (15 elements)

Algorithm

1. Load count from 2200H into register C.
2. Point HL to first data element (2201H).
3. Move first element to A (assume it is the largest).
4. Decrement C (first element already read).
5. Increment HL to next element.
6. Compare current element M with A.
7. If M > A, update A ← M.
8. Increment HL, decrement C.
9. If C ≠ 0, repeat from step 6.
10. Store A at 2300H; HALT.

8085 Assembly Program

;-----------------------------------------------
; Find Largest Number in an Array
; Length at 2200H, Data from 2201H, Result at 2300H
;-----------------------------------------------

        LDA  2200H      ; A <- array length (count)
        MOV  C, A       ; C <- count (loop counter)

        LXI  H, 2201H   ; HL -> start of array

        MOV  A, M       ; A <- first element (assume largest)
        DCR  C          ; one element already read
        INX  H          ; HL -> next element

LOOP:   MOV  B, M       ; B <- current element
        CMP  B          ; A - B ; if A < B, Carry = 1
        JNC  SKIP       ; if A >= B, keep A
        MOV  A, B       ; else A <- larger value B

SKIP:   INX  H          ; next element
        DCR  C          ; decrement counter
        JNZ  LOOP       ; repeat until C = 0

        STA  2300H      ; store largest number
        HLT             ; stop

Dry Run (with Sample Data)

Final Result at 2300H = FFH (255 decimal): the largest element.

Registers Used

Practical Implications of Asynchronous Serial Communication and DTE-DCE Connection (RS-232)

Part 1: Practical Implications of Asynchronous Serial Communication

Asynchronous serial communication has the following practical implications:

1. No Shared Clock Required: Each character is transmitted independently with its own start and stop bits. The transmitter and receiver do not need a common clock signal, making it simpler and cheaper to implement.

2. Start and Stop Bits Overhead: Each data byte requires additional start bit (1 bit) and stop bit (1 or 2 bits), which reduces the effective data throughput compared to synchronous communication.

3. Variable Timing Between Characters: Data characters can be sent at irregular intervals. The receiver re-synchronizes itself at the beginning of each new character using the start bit.

4. Suitable for Low-Speed Communication: Asynchronous communication is well suited for keyboard input, terminals, and modems where data arrives in bursts rather than as a continuous stream.

5. Simple Hardware Implementation: Devices like the 8251A (UART) are used to handle asynchronous serial communication, making it easy to interface with microprocessors.

6. Error Detection: Parity bits can be added for basic error detection, which is important in noisy communication environments.

Part 2: DTE-DCE Connection According to RS-232 Standard

What is RS-232?

• RS-232 stands for Recommended Standard number 232.
• It is the most widely used serial I/O interfacing standard.
• The full RS-232C standard specifies a 25-pin "D" connector, of which 22 pins are used.
• RS-232 is not TTL compatible:
  • Logic 1 is represented by -3V to -25V
  • Logic 0 is represented by +3V to +25V
  • The range -3V to +3V is undefined (transition region)
• Voltage converter ICs such as MC1488 (TTL to RS-232) and MC1489 (RS-232 to TTL) are used for level conversion.

DTE and DCE

DTE-DCE Connection Diagram

        DTE (Computer)              DCE (Modem)
        +-----------+               +-----------+
        |    TxD  --|-------------->|-- RxD     |
        |    RxD  --|<--------------|-- TxD     |
        |    RTS  --|-------------->|-- CTS     |
        |    CTS  --|<--------------|-- RTS     |
        |    DTR  --|-------------->|-- DSR     |
        |    DSR  --|<--------------|-- DTR     |
        |    DCD  --|<--------------|-- DCD     |
        |    GND  --|---------------|-- GND     |
        +-----------+               +-----------+

Key RS-232 Signal Lines

Summary

The RS-232 standard defines the electrical characteristics, signal names, and connector pinout for serial communication between a DTE (such as a computer) and a DCE (such as a modem). The handshaking signals (RTS, CTS, DTR, DSR) ensure that both devices are ready before data transmission begins, making communication reliable even over telephone lines or long-distance links.

Programmable Peripheral Interface 8255A

Purpose of 8255A

The 8255A is a widely used programmable parallel I/O device designed to interface a microprocessor with peripheral devices. Its main purposes are:

• It can be programmed to transfer data under various conditions, ranging from simple I/O to interrupt-driven I/O.
• It is flexible, versatile, and economical, especially when multiple I/O ports are required.
• It is a general-purpose I/O device that can be used with almost any microprocessor (including the 8085).
• It reduces the complexity of interfacing external devices by providing programmable control through a control register.

Ports of 8255A

The 8255A has 24 I/O pins organized into three ports: Port A, Port B, and Port C.

1. Port A (8-bit)

• A full 8-bit parallel port.
• Can be configured as input or output.
• Supports all three operating modes: Mode 0, Mode 1, and Mode 2.
• In Mode 2 (bidirectional), only Port A can be used for bidirectional data transfer.

2. Port B (8-bit)

• A full 8-bit parallel port.
• Can be configured as input or output.
• Supports Mode 0 and Mode 1 only (not Mode 2).

3. Port C (8-bit)

• An 8-bit port that can be used in two ways:
  • As a single 8-bit port for simple I/O.
  • Split into two 4-bit ports:
    • C Upper (C_U) -- upper nibble (bits 7-4)
    • C Lower (C_L) -- lower nibble (bits 3-0)
• Port C is often used to provide control/status signals (handshake signals) for Port A and Port B in Mode 1 and Mode 2 operations.
• Individual bits of Port C can be set or reset using the Bit Set/Reset (BSR) feature.

Data Bus Buffer

The 8255A also contains a three-state bidirectional 8-bit buffer that interfaces it to the system data bus. Data is transmitted or received through this buffer upon execution of input/output instructions by the CPU. Control words and status information are also transferred through this buffer.

Summary Table

The functions of all ports are defined by writing a control word into the control register of the 8255A, making it highly programmable and adaptable to various interfacing requirements.

Kinds of Buses and De-multiplexing in 8085

Part 1: Different Kinds of Buses

A bus is a group of conducting wires (fine thin lines) that connects different parts of a microprocessor system and carries signals between them. There are three types of buses:

1. Address Bus

• A group of conducting wires that carries address only (address of a memory location or I/O port).
• It is unidirectional -- data flows in one direction only: from microprocessor to memory or from microprocessor to I/O devices.
• In the 8085 microprocessor, the address bus is 16-bit wide, meaning it can address 2^16 = 64 KB of memory locations.
• The length of the address bus determines the amount of memory a system can address.

2. Data Bus

• A group of conducting wires that carries data to and from memory or I/O devices.
• It is bidirectional -- data can flow in both directions (read and write).
• In the 8085 microprocessor, the data bus is 8-bit wide, which is why 8085 is called an 8-bit microprocessor.

3. Control Bus

• A group of conducting wires used to generate timing and control signals to control all associated peripherals.
• The microprocessor uses the control bus to determine what operation to perform on the selected memory location.
• Common control signals include:
  • Memory Read
  • Memory Write
  • I/O Read
  • I/O Write
• If the control line is low (no electricity), memory is read; if high, memory is written.

Part 2: De-multiplexing of Buses in 8085

Why De-multiplexing is Carried Out

The 8085 microprocessor has only 40 pins. To reduce the number of pins and keep the chip compact (as a VLSI circuit), Intel multiplexed the lower-order address bus with the data bus on the same set of 8 pins (AD0 -- AD7). This means:

• During the first part (T1 state) of a machine cycle, these pins carry the lower 8 bits of the address (A0 -- A7).
• During the later part (T2, T3 states), the same pins carry 8-bit data (D0 -- D7).

Since address and data share the same lines, they must be separated (de-multiplexed) before use, otherwise the system cannot distinguish between address and data signals.

How De-multiplexing is Carried Out

De-multiplexing is done using a latch (e.g., 74LS373 octal latch):

8085 Pins                Latch (74LS373)          Memory / I/O
AD0 - AD7  ----------->  D0-D7 (Input)
                         Q0-Q7 (Output) -------->  A0 - A7 (Address)
ALE        ----------->  G (Enable)
AD0 - AD7  ----------------------------------------> D0 - D7 (Data)

The upper 8 address bits (A8 -- A15) are available on dedicated pins and do not need de-multiplexing.

Summary