Block Diagram of 80286 and Its Functional Units

Introduction

The Intel 80286 is a 16-bit microprocessor that is an enhanced version of the 8086. It operates at higher speeds and supports protected mode in addition to real mode. The 80286 is internally divided into four independent functional units that operate in a pipeline fashion to increase throughput and processing speed.

Block Diagram of 80286

+------------------+       +------------------+
|                  |       |                  |
|   ADDRESS UNIT   |       |    BUS UNIT      |
|      (AU)        |<----->|      (BU)        |
|                  |       |                  |
| - Segment Regs   |       | - Prefetch Queue |
| - Descriptor     |       | - Bus Control    |
|   Cache Regs     |       | - Address Driver |
| - Adder          |       | - Pipeline/Bus   |
| - Limit Checker  |       |   Size Control   |
| - Protection     |       |                  |
|   Check Unit     |       +------------------+
+------------------+              |
         |                        |
         |    Internal Bus        |
         +------------------------+
         |                        |
+------------------+       +------------------+
|                  |       |                  |
| INSTRUCTION UNIT |       | EXECUTION UNIT   |
|      (IU)        |<----->|      (EU)        |
|                  |       |                  |
| - 6-Byte Prefetch|       | - ALU            |
|   Queue          |       | - Register File  |
| - Instruction    |       | - Barrel Shifter |
|   Decoder        |       | - Multiply/Divide|
| - Decoded        |       |   Unit           |
|   Instruction    |       | - Control Logic  |
|   Queue (3 deep) |       |                  |
+------------------+       +------------------+
         |                        |
         +-------- Internal Bus --+
                       |
              +------------------+
              |   SYSTEM BUSES   |
              | Address Bus (24) |
              | Data Bus (16)    |
              | Control Bus      |
              +------------------+

Functional Units of 80286

The 80286 is divided into four major functional units:

1. Bus Unit (BU)

The Bus Unit is responsible for all external bus operations. It acts as the interface between the processor and the external system buses.

Key components and functions:

• It fetches instruction bytes from memory and places them into the prefetch queue.
• It manages the 24-bit address bus, allowing access to up to 16 MB of physical memory.
• It handles the 16-bit data bus for data transfers.
• It operates independently of the Execution Unit, so it can prefetch instructions while the EU is executing previous instructions.

2. Instruction Unit (IU)

The Instruction Unit is responsible for decoding instructions fetched by the Bus Unit.

Key components and functions:

• It takes instruction bytes from the BU's prefetch queue and decodes them.
• Decoded instructions are placed in a 3-stage decoded instruction queue, which feeds the Execution Unit.
• This pipelining ensures the EU always has a ready decoded instruction, reducing idle time.

3. Execution Unit (EU)

The Execution Unit is responsible for actually executing the decoded instructions provided by the Instruction Unit.

Key components and functions:

• The EU fetches decoded instructions from the IU's decoded queue.
• It performs all arithmetic, logical, shift, and data manipulation operations.
• It communicates with the Address Unit to generate effective addresses for memory operands.
• It uses a dedicated ALU bus for fast internal data transfers.

4. Address Unit (AU)

The Address Unit is responsible for memory address calculation and protection checking in both real mode and protected mode.

Key components and functions:

• In real mode, it adds the segment base (shifted left by 4) to the offset to produce a 20-bit physical address.
• In protected mode, it uses the descriptor cache to obtain the 24-bit base address and adds the offset, producing a full 24-bit physical address.
• It performs protection checks to prevent unauthorized memory access, which is a key feature of the 80286 over the 8086.

Pipeline Operation of the Four Units

The four units operate in a pipelined, overlapping fashion rather than strictly one after another, and this overlap is what gives the 80286 its speed advantage over the 8086:

• The Bus Unit prefetches the next instruction bytes from memory while the current instruction is still being decoded or executed.
• The Instruction Unit decodes the prefetched bytes into micro-operations and keeps up to three decoded instructions queued, so the Execution Unit is rarely left waiting for work.
• The Execution Unit executes one decoded instruction while the Instruction Unit decodes the next one and the Bus Unit fetches the one after that.
• The Address Unit works alongside the Execution Unit, computing and protection-checking physical addresses for memory operands as soon as they are needed, so address translation does not stall the pipeline.

Because fetching, decoding, address computation, and execution proceed concurrently in different units instead of sequentially, the 80286 achieves a higher instruction throughput than the non-pipelined 8086.

Assembly Language Program to Find the Greatest Number in an Array (8085 Microprocessor)

Problem Statement

Find the greatest (maximum) number in an array of 8-bit numbers using the 8085 (8-bit) microprocessor. The array has a minimum size of 20 elements.

Assumptions

Sample Array Data (20 elements at 2201H onwards)

2200H --> 14H       ; count = 20
2201H --> 45H
2202H --> 78H
2203H --> 23H
2204H --> 99H       ; greatest
2205H --> 12H
...  (remaining 15 elements)
2214H --> 67H

Algorithm / Logic

Step 1: Load the count (length) of array into register C
Step 2: Load the first element of array into Accumulator (A)
        This is our initial "maximum" value
Step 3: Decrement counter C by 1 (since first element already loaded)
Step 4: Point HL register pair to the next element (2202H)
Step 5: LOOP:
           Load next element from memory into register B
           Compare A with B  (A - B)
           If A >= B, skip (A is still the maximum)
           If A < B, update A = B (new maximum found)
           Increment HL to point to next element
           Decrement counter C
           If C != 0, repeat LOOP
Step 6: Store the result (maximum value) into 2300H
Step 7: HLT

Assembly Language Program (8085)

        LDA  2200H      ; Load array length (20 = 14H) into Accumulator
        MOV  C, A       ; Move length/count into register C (counter)

        LXI  H, 2201H   ; Point HL to the start of array (first element)
        MOV  A, M       ; Load first element into Accumulator
                        ; Assume first element as the greatest initially

        INX  H          ; Increment HL to point to second element
        DCR  C          ; Decrement counter (one element already loaded)

LOOP:   MOV  B, M       ; Load next array element into register B
        CMP  B          ; Compare Accumulator (current max) with B
                        ; Internally performs A - B and sets flags
        JNC  SKIP       ; Jump to SKIP if A >= B (No Carry means A >= B)
                        ; i.e., current max is still greater or equal

        MOV  A, B       ; If A < B, update Accumulator with new maximum

SKIP:   INX  H          ; Increment HL to point to next memory location
        DCR  C          ; Decrement counter register C by 1
        JNZ  LOOP       ; If counter != 0, jump back to LOOP

        STA  2300H      ; Store the greatest number into memory location 2300H
        HLT             ; Stop the program

Step-by-Step Explanation of Each Instruction

Dry Run / Trace (Partial Example)

Assume array: 45H, 78H, 23H, 99H, 12H ...

Result stored at 2300H = 99H (Greatest number)

Key Notes

CMP instruction in 8085 subtracts the operand from Accumulator without storing the result, but sets the Carry Flag (CY) and Zero Flag (ZF) according to the result: if A = B, CY = 0 and ZF = 1; if A > B, CY = 0 and ZF = 0; if A < B, CY = 1 and ZF = 0.

JNC (Jump if No Carry) is used right after CMP to branch when A >= B, since the Carry flag is cleared only when no borrow was needed.

Using CMP followed by a conditional jump lets the program compare values without altering the Accumulator, which is essential here because the running maximum stored in A must be preserved across every loop iteration until it is actually replaced.

Flag in 8085 Microprocessor

What is a Flag?

A flag is a single-bit flip-flop (1-bit register) that indicates the status or condition of the result stored in the accumulator after the completion of an arithmetic or logical operation. Flags are part of the Flag Register (also called the Program Status Word) inside the ALU. These flip-flops are set (1) or reset (0) according to the data condition of the result in the accumulator.

Flags in 8085 Microprocessor

The 8085 microprocessor has five flags arranged in an 8-bit flag register. The five flags are:

1. Sign Flag (S)

• After an arithmetic or logical operation, if the Most Significant Bit (D7) of the result is 1, the Sign flag is set (S = 1), indicating the result is negative.
• If D7 = 0, the flag is reset (S = 0), indicating the result is positive.
• Example: If result = 10000001 (in 2's complement, a negative number), S = 1.

2. Zero Flag (Z)

• If the result of an operation is zero (00H), the Zero flag is set (Z = 1).
• If the result is non-zero, the flag is reset (Z = 0).
• Example: If 05H - 05H = 00H, then Z = 1.

3. Auxiliary Carry Flag (AC)

• Also called the Half Carry Flag.
• It is set (AC = 1) when there is a carry out from bit D3 to bit D4 (i.e., carry from the lower nibble to the upper nibble) during an arithmetic operation.
• It is primarily used in BCD (Binary Coded Decimal) arithmetic operations (DAA instruction).
• Example: If 0FH + 01H = 10H, a carry is generated from bit 3 to bit 4, so AC = 1.

4. Parity Flag (P)

• After an operation, if the result has an even number of 1s, the Parity flag is set (P = 1) -- indicating even parity.
• If the result has an odd number of 1s, the flag is reset (P = 0) -- indicating odd parity.
• Example: Result = 00000011 (two 1s, even parity), so P = 1.

5. Carry Flag (CY)

• The Carry flag is set (CY = 1) when an arithmetic operation results in a carry out from the MSB (bit D7) during addition, or a borrow during subtraction.
• If there is no carry or borrow, it is reset (CY = 0).
• Example: FFH + 01H = 100H; the carry out of bit 7 sets CY = 1.

Summary Table

These five flags together help the programmer to make conditional decisions (using conditional jump instructions like JZ, JC, JP, etc.) based on the outcome of operations.

Instruction Set and Types of Instructions in 8086 Microprocessor

Definition of Instruction Set

An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions that a microprocessor supports is called the Instruction Set. Each instruction is represented by a binary value called an Op-code (Operation Code).

Types of Instructions in 8086 Microprocessor

The instructions of the 8086 microprocessor are grouped into the following categories:

1. Data Transfer Instructions

These instructions transfer data between registers, memory, and I/O ports.

2. Arithmetic Instructions

These instructions perform arithmetic operations such as addition, subtraction, multiplication, and division.

3. Logical Instructions

These instructions perform bitwise logical operations.

4. Branch / Control Transfer Instructions

These instructions alter the normal sequential flow of program execution.

5. Loop Instructions

These instructions repeat a block of instructions a specified number of times.

6. Rotate and Shift Instructions

These instructions shift or rotate the bits of an operand.

7. Interrupt Instructions

These instructions handle interrupt operations.

Summary

The 8086 instruction set covers data movement, arithmetic, logic, branching, looping, bit manipulation, and interrupt handling, making it a complete and powerful instruction set for general-purpose computing.