ALE Signal and Timing Diagram for LDA 5000H Instruction

Part 1: ALE Signal (Address Latch Enable)

ALE (Address Latch Enable) is a control signal generated by the 8085 microprocessor. It is an active HIGH output signal that is used to demultiplex the lower-order address bus from the data bus.

Why ALE is Needed:

The 8085 has a multiplexed address/data bus. The lower 8 bits of the address (A0-A7) share the same physical pins as the 8-bit data bus (AD0-AD7). To separate the address from the data, the ALE signal is used.

How ALE Works:

• ALE goes HIGH at the beginning of the first T-state (T1) of every machine cycle.
• During T1, when ALE is HIGH, the lower 8-bit address (A0-A7) is present on the AD0-AD7 lines.
• An external latch (e.g., 74LS373) captures and holds this lower address when ALE goes LOW.
• After ALE goes LOW (from T2 onwards), the AD0-AD7 lines are used as the data bus.
• The higher-order address bits (A8-A15) remain on the dedicated address bus throughout the machine cycle.

In short: ALE = 1 means address is on AD0-AD7; ALE = 0 means data is on AD0-AD7.

Part 2: LDA 5000H Instruction

Meaning:

LDA 5000H means Load Accumulator Direct from memory address 5000H.

• The contents of memory location 5000H are loaded into the Accumulator (A).
• It is a 3-byte instruction: Opcode (3AH) + Low byte of address (00H) + High byte of address (50H).

Machine Cycles Involved:

LDA 5000H consists of 4 machine cycles and a total of 13 T-states:

Part 3: Timing Diagram for LDA 5000H

Assume the instruction starts at memory address 2050H.

         MC1 (Opcode Fetch)      MC2 (Mem Read)    MC3 (Mem Read)    MC4 (Mem Read)
         T1   T2   T3   T4       T1   T2   T3       T1   T2   T3      T1   T2   T3
          |    |    |    |        |    |    |         |    |    |       |    |    |
CLK    __| |__| |__| |__| |____| |__| |__| |_______| |__| |__| |_____| |__| |__| |__

ALE    _____|   |_________________|   |_______________|   |_____________|   |________
       HIGH at T1 of each MC

A8-A15 --[  20H  ]---------------[  20H  ]----------[  20H  ]--------[  50H  ]------
       (High order address, stable throughout each MC)

AD0-A7 -[2050H lo]-[  3AH  ]-----[2051H lo]-[00H]---[2052H lo]-[50H]-[00H lo]-[data]
        addr(T1)   data(T2-T4)    addr(T1)  data     addr(T1)  data   addr(T1) data

IO/M   ___________________________________________  LOW (Memory operation throughout)

RD     ________|___________________|_______________|_______________|________________
               LOW during read     LOW             LOW             LOW
               (T2-T3)

Cleaner Representation:

CLK:    _|-|_|-|_|-|_|-|_  _|-|_|-|_|-|_  _|-|_|-|_|-|_  _|-|_|-|_|-|_
        T1  T2  T3  T4      T1  T2  T3      T1  T2  T3      T1  T2  T3

        |<---- MC1 ------->|<--- MC2 ---->|<--- MC3 ---->|<--- MC4 ---->|

ALE:    |HIGH|_____________|HIGH|_________|HIGH|_________|HIGH|_________|

A8-A15: |  20H (high byte of 2050H)  |20H |     |20H |     |  50H      |

AD0-AD7:|2050H|  3AH (opcode) |2051H|00H |2052H|50H  |5000H| DATA(Acc) |
        |addr | data          |addr |data |addr |data |addr | data      |

IO/M:   |___________ LOW (Memory) ___________________________________|

RD:     |    |___|   |    |___|    |    |___|    |    |___|           |
              active        active        active        active
              LOW           LOW           LOW           LOW

Part 4: Explanation of Each Machine Cycle

Machine Cycle 1 - Opcode Fetch (4 T-states):

• T1: PC (2050H) is placed on address bus. ALE goes HIGH. Lower address (50H) latched externally.
• T2: ALE goes LOW. RD goes LOW.

LHLD & SHLD Instructions + Sum of Data Array Program

STEP 1 - EXTRACT (Given Data)

• Number of data values: 10 (0AH)
• Data type: 8-bit each
• Data starting address: 6000H (so 6000H to 6009H)
• Sum storage address: 9500H
• Carry storage address: implied 9501H (next location)

All required data is present.

STEP 2 - SOLVE

Part 1: LHLD and SHLD Instructions

LHLD (Load H-L pair Direct)

A 3-byte instruction that loads the contents of two consecutive memory locations directly into the HL register pair.

Syntax: LHLD address

Operation:

• $L \leftarrow M[address]$
• $H \leftarrow M[address+1]$

Example: LHLD 2200H - if 2200H = 45H and 2201H = 32H, then after execution $L = 45H$, $H = 32H$.

Size: 3 bytes, Machine cycles: 5, T-states: 16

SHLD (Store H-L pair Direct)

A 3-byte instruction that stores the contents of the HL register pair into two consecutive memory locations.

Syntax: SHLD address

Operation:

• $M[address] \leftarrow L$
• $M[address+1] \leftarrow H$

Example: SHLD 2302H - if $H = 32H$, $L = 45H$, then 2302H = 45H, 2303H = 32H.

Size: 3 bytes, Machine cycles: 5, T-states: 16

Part 2: Assembly Language Program

Algorithm

1. Initialize carry register $C = 00H$
2. Initialize counter $B = 0AH$ (10 items)
3. Point HL to 6000H
4. Clear accumulator ($A = 00H$)
5. Add memory content to A; if carry occurs, increment C
6. Advance pointer, decrement counter, repeat until zero
7. Store sum at 9500H, carry at 9501H

Program

; Sum of 10 eight-bit data stored from 6000H
; Sum -> 9500H, Carry -> 9501H

        MVI C, 00H      ; carry counter = 0
        MVI B, 0AH      ; counter = 10
        LXI H, 6000H    ; HL points to first data
        SUB A           ; A = 0 (clear accumulator, clears CY)

BACK:   ADD M           ; A = A + [HL]
        JNC SKIP        ; if no carry, skip
        INR C           ; else increment carry register

SKIP:   INX H           ; next memory location
        DCR B           ; decrement counter
        JNZ BACK        ; repeat until counter = 0

        STA 9500H       ; store sum
        MOV A, C        ; move carry to A
        STA 9501H       ; store carry

        HLT             ; halt

Explanation

Key Points

• Register C accumulates the number of carries, forming the high byte of the 16-bit result. Since each byte is at most FFH, the maximum sum of 10 bytes is $10 \times 255 = 2550 = 09F6H$, so C never exceeds 09H: a single carry register suffices.
• SUB A clears the accumulator and also resets the carry flag before the loop.

Result: Low byte of sum stored at 9500H, carry (high byte) stored at 9501H.

Note: the problem does not explicitly state 9501H for the carry, but "starting from 9500H" naturally implies the next byte (9501H), so that assumption is reasonable and standard.

ALP to Convert String 'computer science' to Upper Case (16-bit Microprocessor / 8086)

Concept

In ASCII, lowercase letters range from 61H ('a') to 7AH ('z') and uppercase letters range from 41H ('A') to 5AH ('Z'). To convert lowercase to uppercase, we subtract 20H from the ASCII value of each lowercase character.

Spaces and other non-alphabetic characters are left unchanged.

Assembly Language Program

.MODEL SMALL
.STACK 100H

.DATA
    STRING DB 'computer science', '$'   ; Define the string with $ terminator
    LEN    DW 16                        ; Length of the string (16 characters)

.CODE
MAIN PROC
    MOV AX, @DATA          ; Load address of DATA segment into AX
    MOV DS, AX             ; Initialize Data Segment register

    MOV SI, OFFSET STRING  ; SI points to the start of the string
    MOV CX, LEN            ; CX = loop counter = length of string

BACK:
    MOV AL, [SI]           ; Load current character into AL

    CMP AL, 'a'            ; Compare AL with 'a' (61H)
    JB  SKIP               ; If AL < 'a', not a lowercase letter, skip

    CMP AL, 'z'            ; Compare AL with 'z' (7AH)
    JA  SKIP               ; If AL > 'z', not a lowercase letter, skip

    SUB AL, 20H            ; Convert lowercase to uppercase by subtracting 20H
    MOV [SI], AL           ; Store the converted character back into memory

SKIP:
    INC SI                 ; Move SI to point to next character
    LOOP BACK              ; Decrement CX and repeat if CX != 0

    ; Display the converted string
    MOV DX, OFFSET STRING  ; Load address of converted string into DX
    MOV AH, 09H            ; DOS function 09H: display string
    INT 21H                ; Call DOS interrupt

    MOV AX, 4C00H          ; DOS function 4CH: terminate program
    INT 21H

MAIN ENDP
END MAIN

Step-by-Step Explanation

Example Conversion

Output: COMPUTER SCIENCE

Vectored Interrupt, Maskable and Non-Maskable Interrupts in 8085

Vectored Interrupt

A vectored interrupt is an interrupt in which the interrupting device not only signals the processor for attention but also identifies itself by providing the address (vector) of its Interrupt Service Routine (ISR) directly.

• When a vectored interrupt occurs, the microprocessor automatically jumps to a fixed, pre-defined memory address associated with that interrupt, without needing to poll or search for the source.
• This makes the response faster and more efficient.

Example: In the 8085, interrupts like TRAP, RST 5.5, RST 6.5, RST 7.5 are vectored interrupts because each one has a fixed call address in memory.

In contrast, a non-vectored interrupt (like INTR) does not provide the address directly; the processor must determine the ISR address through external hardware.

Interrupts in 8085 Microprocessor

The 8085 has 5 hardware interrupt pins:

1. Maskable Interrupts

• A maskable interrupt is one that can be enabled or disabled (masked) by the programmer using software instructions.
• In 8085, the EI (Enable Interrupt) and DI (Disable Interrupt) instructions are used to enable or disable maskable interrupts.
• When the processor is busy with a critical task, it can ignore (mask) these interrupts temporarily.
• The response to a maskable interrupt can be immediate or delayed.

Maskable interrupts in 8085:

• INTR - General purpose maskable interrupt; requires external hardware to supply the restart address.
• RST 5.5 - Vectored; calls address 002CH
• RST 6.5 - Vectored; calls address 0034H
• RST 7.5 - Vectored; calls address 003CH (highest priority among maskable)

These can also be individually masked using the SIM (Set Interrupt Mask) instruction.

2. Non-Maskable Interrupt

• A non-maskable interrupt is one that cannot be disabled or ignored by the programmer. The processor must respond to it immediately regardless of the state of the interrupt enable flag.
• It is used for emergency or critical situations such as power failure.

Non-maskable interrupt in 8085:

• TRAP - It is the only non-maskable interrupt in 8085.
  • It has the highest priority among all interrupts.
  • It is both edge-triggered and level-triggered (making it very reliable).
  • It calls the fixed address 0024H.
  • It cannot be masked by EI/DI instructions or SIM instruction.

Summary Table

Register Organization in 80386 Microprocessor

Register Organization of 80386 Microprocessor

The Intel 80386 is a 32-bit microprocessor. Its registers are organized into the following groups:

1. General Purpose Registers (32-bit)

These registers are used for arithmetic, logical, and data transfer operations.

• Each 32-bit register can also be accessed as a 16-bit register (AX, BX, CX, DX, SP, BP, SI, DI).
• AX, BX, CX, DX can further be split into 8-bit high and low bytes (AH/AL, BH/BL, CH/CL, DH/DL).

2. Segment Registers (16-bit)

The 80386 uses segmented memory model. It has 6 segment registers:

3. Control Registers

Important flags in EFLAGS:

• CF - Carry Flag
• ZF - Zero Flag
• SF - Sign Flag
• OF - Overflow Flag
• DF - Direction Flag (for string operations)
• IF - Interrupt Enable Flag

4. System Registers

These are used for memory management and protection in protected mode:

Summary Diagram

80386 Registers
├── General Purpose (EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP) -- 32-bit
├── Segment Registers (CS, DS, SS, ES, FS, GS) -- 16-bit
├── Control Registers (EIP, EFLAGS) -- 32-bit
└── System Registers (CR0-CR3, GDTR, LDTR, IDTR, TR)

Key Feature

The 80386 supports backward compatibility - programs written for 8086/80286 can run on 80386 because the lower 16-bit portions of the registers (AX, BX, etc.) are preserved within the 32-bit extended registers (EAX, EBX, etc.).

Limitations of Parallel Communication and Operation Modes of 8255A PPI

Part 1: Limitations of Parallel Communication

Parallel communication transmits multiple bits simultaneously over multiple lines, but it has the following limitations:

1. Cost: Requires more wires/lines (one for each bit), making it more expensive than serial communication.
2. Distance Limitation: Suitable only for short distances (typically within a few meters) because signal degradation and crosstalk increase with distance.
3. Crosstalk: Interference between adjacent parallel lines causes data errors, especially at high speeds over longer distances.
4. Synchronization Problem: All bits must arrive at the same time; skew (timing differences between lines) can cause data corruption.
5. Cable Bulk: Multiple wires make the cable thick, heavy, and difficult to manage.
6. Higher Power Consumption: More lines mean more drivers and receivers, consuming more power.
7. Not Suitable for Long Distance: Cannot be used effectively for long-distance communication unlike serial communication.

Part 2: Operation Modes of 8255A PPI

csc167-8255-block

The 8255A Programmable Peripheral Interface (PPI) has three ports: Port A, Port B, and Port C. It operates in the following modes, determined by the Control Word Register (bit D7 = 1 for I/O mode):

Mode 0: Basic Input/Output Mode

• This is the simplest mode of operation.
• Port A, Port B, and both halves of Port C (upper and lower) can be independently configured as input or output.
• No handshaking signals are required.
• Data is simply written to or read from the ports.
• Suitable for simple I/O operations like reading switches or driving LEDs.
• Port C can be split: upper nibble (PC7-PC4) and lower nibble (PC3-PC0) configured separately.

Example use: Connecting keyboards, displays, or simple peripheral devices.

Mode 1: Strobed Input/Output Mode (Handshaking Mode)

• Used for Port A and Port B only.
• Port C lines are used as handshaking/control signals for Port A and Port B.
• Data transfer occurs with synchronization signals (handshaking).
• Two sub-modes:
  • Mode 1 Input: Uses signals like STB (Strobe), IBF (Input Buffer Full), and INTR (Interrupt Request).
  • Mode 1 Output: Uses signals like OBF (Output Buffer Full), ACK (Acknowledge), and INTR.
• Suitable when the peripheral needs to signal readiness before data transfer.

Example use: Interfacing with printers or other devices requiring handshaking.

Mode 2: Bidirectional Bus Mode

• Available for Port A only.
• Port A acts as a bidirectional 8-bit data bus (both input and output on the same port).
• Port C lines (PC7-PC3) are used as control/handshaking signals for Port A.
• Port B can still operate in Mode 0 or Mode 1 independently.
• Suitable for communication between two microprocessors or complex peripherals.

Example use: Data transfer between two CPUs sharing a common bus.

Bit Set/Reset (BSR) Mode

• This is a special mode for Port C only.
• When bit D7 = 0 in the control word, Port C operates in BSR mode.
• Individual bits of Port C can be set (1) or reset (0) using a specific control word.
• This does not affect Port A or Port B operations.
• Useful for generating control signals or flags on individual pins.

Summary Table

Descriptor and Segment Descriptor in 80286 Physical Address Conversion

What is a Descriptor?

A descriptor is a data structure (8 bytes long) stored in memory that contains all the necessary information about a memory segment. In the protected mode of the 80286 microprocessor, segment registers do not hold the physical base address directly; instead, they hold a selector that points to a descriptor in a descriptor table.

A segment descriptor contains three key fields:

Memory Access in Protected Mode (80286)

In the 80286 protected mode, physical address conversion involves the following steps:

Step 1: Selector in Segment Register

When a memory reference is made, the segment register (CS, DS, SS, ES) contains a selector (not a direct address). The selector specifies:

• The index into the descriptor table
• The table indicator (GDT or LDT)
• The requested privilege level (RPL)

Step 2: Accessing the Descriptor Table

The selector is used to locate the appropriate segment descriptor from either:

• GDT (Global Descriptor Table) -- pointed to by the GDTR register
• LDT (Local Descriptor Table) -- pointed to by the LDTR register

The CPU reads the 8-byte descriptor from the table.

Step 3: Protection Check

The CPU checks the access rights byte in the descriptor to verify:

• The segment is present in memory
• The current privilege level is allowed to access the segment
• The offset does not exceed the segment limit

If any check fails, a protection fault is generated.

Step 4: Physical Address Calculation

Once the descriptor is validated, the 24-bit base address is extracted from the descriptor. The physical address is calculated as:

Physical Address = Segment Base Address (from descriptor) + Effective Offset

Note: The effective address (offset) is added with the segment base address to calculate the linear address. This linear address is used directly as the physical address if the paging unit is disabled.

Diagram of Address Conversion

Segment Register
+------------------+
|    Selector      |
+------------------+
        |
        | Index into Descriptor Table
        v
+---------------------------+
| Descriptor Table (GDT/LDT)|
|  [Base Addr | Limit | AR] |
+---------------------------+
        |
        | 24-bit Base Address
        v
   Base Address
        +
   Effective Offset (from instruction)
        =
   Linear Address = Physical Address (paging disabled)

Summary

Thus, the segment descriptor plays a central role in the 80286 protected mode by providing the base address, enforcing memory limits, and implementing privilege-based memory protection during physical address conversion.

Short Notes: Flags in 8085 MPU and DMA

a. Flags in 8085 MPU

Flags are special flip-flop circuits within the Flag Register (also called the Program Status Word) of the 8085 microprocessor. They are set (1) or reset (0) automatically based on the result of arithmetic and logical operations performed by the ALU. They indicate the status of the accumulator and other registers after the completion of an operation.

The 8085 MPU uses 5 flags, arranged in an 8-bit flag register:

The Five Flags:

1. Sign Flag (S)

   • Set to 1 if the result of an operation is negative (i.e., the MSB/D7 bit of the result is 1).
   • Reset to 0 if the result is positive.

2. Zero Flag (Z)

   • Set to 1 if the result of an operation is zero.
   • Reset to 0 if the result is non-zero.

3. Auxiliary Carry Flag (AC)

   • Set to 1 if there is a carry out from bit D3 to bit D4 (carry from the lower nibble to the upper nibble).
   • Primarily used in BCD (Binary Coded Decimal) arithmetic operations.

4. Parity Flag (P)

   • Set to 1 if the result contains an even number of 1s (even parity).
   • Reset to 0 if the result contains an odd number of 1s (odd parity).

5. Carry Flag (CY)

   • Set to 1 if an arithmetic operation generates a carry out from the MSB (D7) or requires a borrow.
   • Used in multi-byte addition and subtraction operations.

These flags are essential for conditional branching instructions (e.g., JZ, JNZ, JC, JNC) which allow the program to make decisions based on the result of previous operations.

b. DMA (Direct Memory Access)

DMA (Direct Memory Access) is a technique that allows I/O devices to transfer data directly to or from memory without the involvement of the CPU for each byte of data transferred.

Need for DMA:

• Normally, data transfer between memory and I/O devices is managed by the CPU, which wastes CPU time.
• For large and high-speed data transfers (e.g., disk drives, video, network), DMA provides a much faster and efficient method.

How DMA Works:

1. The I/O device requests a DMA transfer by sending a signal to the DMA Controller (DMAC).
2. The DMAC sends a HOLD request to the CPU.
3. The CPU completes its current operation, then sends a HLDA (Hold Acknowledge) signal and releases the buses (address, data, and control buses).
4. The DMAC takes control of the buses and transfers data directly between the I/O device and memory.
5. After the transfer is complete, the DMAC releases the buses and the CPU resumes normal operation.

Key Components:

• DMA Controller (DMAC): A dedicated chip (e.g., Intel 8257) that manages the transfer.
• HOLD and HLDA pins of the 8085 are used for DMA handshaking.

Advantages of DMA:

• Fast data transfer at memory speed.
• CPU is free to perform other tasks (or is only briefly paused).
• Efficient for bulk data transfers.

Disadvantage:

• Requires additional hardware (DMAC chip), increasing system cost and complexity.

Summary Table: