2077

BIT103 · TU past paper

Digital Logic 2077 question paper

The complete TU 2077 exam paper for Digital Logic (BIT103), all 12 questions with solved model answers written to the mark scheme.

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  1. 110 marksBCD to decimal decoderAnswer

    What is Decoder? Design BCD to Decimal Decoder with Truth Table and Logic Diagram [10]

    A decoder is a combinational logic circuit that converts an n-bit binary input code into a maximum of 2ⁿ unique output lines, where only one output is active (HIGH) at a time for each valid input combination. - It is essentially a minter...

  2. 210 marksCombinational circuit design methodologyAnswer

    Design a combinational circuit whose input is a four-bit number and output is 2's complement of the input number.[10]

    Design of Combinational Circuit for 2's Complement of a 4-bit Number

    Concept

    The 2's complement of a binary number is obtained by:

    1. Taking the 1's complement (inverting all bits), then
    2. Adding 1 to the result

    For a 4-bit input A = A₃A₂A₁A₀, the output is S = S₃S₂S₁S₀


    Truth Table

    The 2's complement of N is: S = 2⁴ - N = 16 - N

    A₃A₂A₁A₀S₃S₂S₁S₀
    00000000
    00011111
    00101110
    00111101
    01001100
    01011011
    01101010
    01111001
    10001000
    10010111
    10100110
    10110101
    11000100
    11010011
    11100010
    11110001

    Logical Design Approach

    The copy-and-invert rule

    There is a well-known pattern for the 2's complement:

    Copy all bits from the right up to and including the first 1, then invert every bit above it.

    The rule follows from the definition. Complementing every bit gives $\overline{A_i}$, and adding 1 to that propagates a carry only while the complemented bits are 1, that is only while the original bits are 0. So with $B_i = \overline{A_i}$ and an initial carry $C_0 = 1$:

    $$S_i = B_i \oplus C_i = \overline{A_i} \oplus C_i$$

    $$C_{i+1} = B_i \cdot C_i = \overline{A_i} \cdot C_i$$

    The complement must appear in BOTH equations. Using $A_i$ rather than $\overline{A_i}$ builds an incrementer that computes $A + 1$, not the 2's complement.


    Boolean Expressions

    Carry Equations:

    $$C_0 = 1$$

    $$C_1 = \overline{A_0} \cdot C_0 = \overline{A_0}$$

    $$C_2 = \overline{A_1} \cdot C_1 = \overline{A_1} \cdot \overline{A_0} = \overline{A_1 + A_0}$$

    $$C_3 = \overline{A_2} \cdot C_2 = \overline{A_2 + A_1 + A_0}$$

    Output Equations:

    Since $\overline{x} \oplus \overline{y} = x \oplus y$, each output simplifies neatly:

    $$\boxed{S_0 = \overline{A_0} \oplus 1 = A_0}$$

    $$\boxed{S_1 = \overline{A_1} \oplus \overline{A_0} = A_1 \oplus A_0}$$

    $$\boxed{S_2 = A_2 \oplus (A_1 + A_0)}$$

    $$\boxed{S_3 = A_3 \oplus (A_2 + A_1 + A_0)}$$

    Read together these are exactly the copy-and-invert rule: $S_0$ is a plain copy of $A_0$, and each higher bit is inverted precisely when some lower bit is 1, which is when the first 1 has already been passed.


    Circuit Diagram

    A0 ──────────────────────────────────────────────── S0   (direct connection)
    
    A1 ──┐
         XOR ─────────────────────────────────────────── S1
    A0 ──┘
    
    A1 ──┐
         OR ── P1 = A1 + A0 ──┐
    A0 ──┘                    XOR ───────────────────── S2
    A2 ───────────────────────┘
    
    A2 ──┐
         OR ── P2 = A2 + P1 ──┐
    P1 ──┘                    XOR ───────────────────── S3
    A3 ───────────────────────┘
    

    Gates required: two OR gates (the second reuses the output of the first) and three XOR gates. $S_0$ needs no gate at all, so seven gate inputs in total realise the whole circuit.


    Verification

    Take A = 0110 (decimal 6). Then $A_0 = 0$, $A_1 = 1$, $A_2 = 1$, $A_3 = 0$, so

    $$S_0 = A_0 = 0$$

    $$S_1 = A_1 \oplus A_0 = 1 \oplus 0 = 1$$

    $$S_2 = A_2 \oplus (A_1 + A_0) = 1 \oplus 1 = 0$$

    $$S_3 = A_3 \oplus (A_2 + A_1 + A_0) = 0 \oplus 1 = 1$$

    The output is S = 1010 (decimal 10), and $16 - 6 = 10$, which agrees with the truth table row for 0110.

    Checking the two extremes as well: for $A = 0000$ every OR term is 0 and every output is 0, which is correct because the 2's complement of zero is zero; for $A = 1111$ the outputs are $1, 0, 0, 0$ read from $S_0$, giving $S = 0001$, and $16 - 15 = 1$.


    Conclusion

    The 2's complement circuit does not need a full adder chain. Because the carry out of the increment propagates only while the complemented bits are 1, each output reduces to $S_i = \overline{A_i} \oplus C_i$ with $C_{i+1} = \overline{A_i} \cdot C_i$ and $C_0 = 1$, which flattens to a copy of $A_0$ and an XOR of each higher bit with the OR of all bits below it. Two OR gates and three XOR gates are enough.

  3. 310 marksRing counter and Johnson counterAnswer

    What is ring counter? Explain ring counter with diagram, timing sequence and timing diagram.[10]

    A ring counter is a type of shift register in which the output of the last flip-flop is connected back (fed back) to the input of the first flip-flop, forming a closed loop or "ring." It is also called a circular shift register. A single...

  4. 45 marksNumericalFractional number conversionsAnswer

    Convert (1011.110) into decimal and hexadecimal. [5]

    Convert $(1011.110)_2$ to Decimal and Hexadecimal

    Step 1: Extract Given Data

    Given data:

    • Binary number: $1011.110_2$
    • Integer part: $1011$
    • Fractional part: $110$

    Required conversions: to decimal (base 10) and to hexadecimal (base 16).


    Step 2: Solve

    Part A: Binary to Decimal

    Integer part $1011$:

    $$1\times2^3 + 0\times2^2 + 1\times2^1 + 1\times2^0 = 8 + 0 + 2 + 1 = 11$$

    Fractional part $.110$:

    $$1\times2^{-1} + 1\times2^{-2} + 0\times2^{-3} = 0.5 + 0.25 + 0 = 0.75$$

    Combine:

    $$(1011.110)2 = 11 + 0.75 = (11.75){10}$$


    Part B: Binary to Hexadecimal

    Group into blocks of 4 bits from the binary point outward, padding with zeros.

    Integer part: $1011$ (already 4 bits)

    $$1011_2 = 8+2+1 = 11 = B$$

    Fractional part: $110 \rightarrow$ pad right to $1100$

    $$1100_2 = 8+4 = 12 = C$$

    Result:

    $$(1011.110)2 = (B.C){16}$$

    Check via decimal: $11.75_{10} = B + 0.75$. Fraction $0.75 = \frac{12}{16} = 0.C_{16}$. ✓


    Summary

    FromToResult
    $(1011.110)_2$Decimal$(11.75)_{10}$
    $(1011.110)_2$Hexadecimal$(B.C)_{16}$
  5. 55 marksNumericalBinary subtraction using complementsAnswer

    Substract (1011.11- 1010.10) using 2's and l's complement. [5]

    • Minuend: $1011.112$ - Subtrahend: $1010.102$ - Operation: $1011.11 - 1010.10$ Decimal check of inputs: - $1011.11 = 8 + 2 + 1 + 0.5 + 0.25 = 11.75$ - $1010.10 = 8 + 2 + 0.5 = 10.50$ - Expected difference $= 11.75 - 10.50 = 1.25$ --- St...
  6. 65 marksNumericalMinterms and maxterms representationAnswer

    Express the given function in sum of minterms. F = y'z + wxy' + wzx' + w'x'z' [5]

    Variables (4): $w, x, y, z$ in order (MSB = $w$, LSB = $z$). $$F = y'z + wxy' + wzx' + w'x'z'$$ Total possible minterms: $2^4 = 16$ ($m0$ to $m{15}$). Use $A = A(B + B') = AB + AB'$ for missing variables. $$y'z = (w+w')(x+x')y'z = wxy'z ...

  7. 75 marksNumericalDon't care conditions in K-mapsAnswer

    Simplify the Boolean function using don't care conditions d in sum of products form. and product of sums form $F(A, B, C, D) = \pi(1, 3, 7, 8, 12) \text{ and } \pi d(5, 10, 13, 14)$ [5]

    The function is given in Product of Sums (POS) form (uses $\pi$): - Maxterms (F = 0): $\pi(1, 3, 7, 8, 12)$ - Don't care terms: $d(5, 10, 13, 14)$ - Variables: $A, B, C, D$ (4 variables, cells 0-15) Minterms (F = 1) = remaining cells =

  8. 85 marksHalf subtractor and full subtractor designAnswer

    Implement a full subtractor with two half subtractors and one OR Gate. [5]

    A Half Subtractor subtracts two single bits (A and B) and produces: - Difference: D = A ⊕ B - Borrow: Bout = A'B A B D Bout ---------------- 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 --- A Full Subtractor subtracts three bits: A (minuend), B (subt...

  9. 95 marksSR latch and clocked RS flip-flopAnswer

    Define SR latch with logic diagram and truth table. [5]

    An SR Latch (Set-Reset Latch) is a basic bistable multivibrator circuit that can store one bit of information. It has two inputs: - S (Set) - used to set the output Q to 1 - R (Reset) - used to reset the output Q to 0 It has two compleme...

  10. 105 marksRipple counters and synchronous countersAnswer

    Compare the logic of synchronous counter and ripple counter. [5]

    Logic of Operation: - Only the first flip-flop receives the external clock pulse directly. - Each subsequent flip-flop is triggered by the output (Q) of the previous flip-flop. - The clock signal "ripples through" from one flip-flop to t...

  11. 115 marksShift register types and operationAnswer

    Define shift register with its types. [5]

    A shift register is a sequential logic circuit consisting of a cascade of flip-flops connected in series, where data is stored and shifted (moved) from one flip-flop to the next on each clock pulse. It is used for temporary data storage,...

  12. 125 marksParity generator and checkerAnswer

    Write short notes on: a.) Parity generator b.) State Diagram [2.5+2.5]

    Definition: A parity generator is a combinational logic circuit that generates a parity bit (either even or odd) to be appended to a binary data word for the purpose of error detection during data transmission. Working Principle: - The c...