BIT103 · TU past paper
Digital Logic 2078 question paper
The complete TU 2078 exam paper for Digital Logic (BIT103), all 13 questions with solved model answers written to the mark scheme.
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- 110 marksCombinational circuit design methodologyHideAnswer
Design a combinational circuit with four inputs and one output. The output is equal to 1 when (i) all the inputs are equal to 1 or (ii) none of the inputs are equal to 1 or (iii) an odd number of inputs are equal to 1.[10]
Let the four inputs be A, B, C, D and output be F. Output F = 1 when: 1. All inputs are 1 (i.e., ABCD = 1111) 2. None of the inputs are 1 (i.e., ABCD = 0000) 3. An odd number of inputs are 1 (i.e., exactly 1 or exactly 3 inputs are 1) --...
- 25 marksNumericalDecoder design and operationHideAnswer
Implement the following function: F = Σ\SigmaΣ(0,1,3,4,5,8,9,10,15) using i) Decoder ii) Multiplexer iii) PLA[5]
Implementation of F = Σ(0,1,3,4,5,8,9,10,15)
STEP 1 - Given Data
- Function: $F(A,B,C,D) = \Sigma m(0,1,3,4,5,8,9,10,15)$
- 4 variables: A (MSB), B, C, D (LSB)
- Minterms where F = 1: {0, 1, 3, 4, 5, 8, 9, 10, 15}
- Minterms where F = 0: {2, 6, 7, 11, 12, 13, 14}
Truth Table
m A B C D F 0 0 0 0 0 1 1 0 0 0 1 1 2 0 0 1 0 0 3 0 0 1 1 1 4 0 1 0 0 1 5 0 1 0 1 1 6 0 1 1 0 0 7 0 1 1 1 0 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 0 12 1 1 0 0 0 13 1 1 0 1 0 14 1 1 1 0 0 15 1 1 1 1 1
STEP 2 - SOLVE
i) Using Decoder (4-to-16 Decoder)
A 4-to-16 decoder produces all 16 minterms on its outputs $D_0 \ldots D_{15}$. Feed the minterm outputs where F = 1 into an OR gate.
$$F = D_0 + D_1 + D_3 + D_4 + D_5 + D_8 + D_9 + D_{10} + D_{15}$$
A,B,C,D --> [4-to-16 Decoder] outputs D0,D1,D3,D4,D5,D8,D9,D10,D15 --> [9-input OR gate] --> F(If active-low decoder outputs are used, a 9-input NAND gate is used instead.)
ii) Using Multiplexer (8-to-1 MUX)
Use A, B, C as select lines ($S_2=A,,S_1=B,,S_0=C$) and D as data variable.
A B C m(D=0) / m(D=1) F,F Input 000 m0=1, m1=1 1,1 1 001 m2=0, m3=1 0,1 D 010 m4=1, m5=1 1,1 1 011 m6=0, m7=0 0,0 0 100 m8=1, m9=1 1,1 1 101 m10=1, m11=0 1,0 D' 110 m12=0,m13=0 0,0 0 111 m14=0,m15=1 0,1 D MUX input connections:
$$I_0=1,; I_1=D,; I_2=1,; I_3=0,; I_4=1,; I_5=D',; I_6=0,; I_7=D$$
iii) Using PLA
Minimize using K-map.
CD AB 00 01 11 10 00 | 1 1 1 0 01 | 1 1 0 0 11 | 0 0 1 0 10 | 1 1 0 1Grouping SOP terms:
- P1: $A'C'$ → cells 00-00,00-01,01-00,01-01 = m0,m1,m4,m5 ✓
- P2: $B'C'$ → m0,m1,m8,m9 (00-00,00-01,10-00,10-01) ✓
- P3: $A'B'D$ → m1,m3 (00-01,00-11) ✓
- P4: $B'C D'$ → m10 (10-10); pair with m8? m8=10-00 no. Use $A B' C D'$... check m10 alone. Pair m10 with m2(=0) not allowed. So $m10 = AB'CD'$ (single cell).
- P5: $ABCD$ → m15 (single cell)
Verify coverage:
- P1 covers 0,1,4,5
- P2 covers 0,1,8,9
- P3 covers 1,3
- P4 covers 10
- P5 covers 15
Union = {0,1,3,4,5,8,9,10,15} ✓ all minterms covered, no extra.
$$\boxed{F = A'C' + B'C' + A'B'D + AB'CD' + ABCD}$$
PLA Programming Table (5 product terms, inputs A,B,C,D, one output F):
Product A B C D F $A'C'$ 0 - 0 - 1 $B'C'$ - 0 0 - 1 $A'B'D$ 0 0 - 1 1 $AB'CD'$ 1 0 1 0 1 $ABCD$ 1 1 1 1 1 (AND array programs the 5 product terms; OR array connects all 5 to output F.)
Common mistake: grouping the PLA K-map carelessly, for example placing $m_{10}$ in an $AB'$ pair that covers 10. The minimized expression above is the correct grouping. The MUX and decoder parts are straightforward by comparison.
- 310 marksRace condition and triggering methodsHideAnswer
What do you mean by race condition in JK Flip Flop?Mention the methods to overcome race condition in JK Flip Flop. Explain Master Slave Flip-flop using JK flip flop with logic circuit, truth table and timing diagram.[3+7]
Note: No curriculum notes were found for this topic. The following answer is based on standard digital electronics content as taught in BSc CSIT curriculum. --- A race condition (also called racing or critical race) in a JK flip-flop occ...
- 45 marksNumericalFractional number conversionsHideAnswer
Convert (1011.110) into decimal. and hexadecimal [5]
Convert $(1011.110)_2$ to Decimal and Hexadecimal
Given Data
- Binary number: $(1011.110)_2$
- Integer part: $1011$
- Fractional part: $.110$
Part 1: Binary to Decimal
Multiply each bit by its positional weight (power of 2) and sum.
Integer part: $1011$
$$1 \times 2^3 + 0 \times 2^2 + 1 \times 2^1 + 1 \times 2^0 = 8 + 0 + 2 + 1 = 11$$
Fractional part: $.110$
$$1 \times 2^{-1} + 1 \times 2^{-2} + 0 \times 2^{-3} = 0.5 + 0.25 + 0 = 0.75$$
Total
$$11 + 0.75 = \boxed{11.75_{10}}$$
Part 2: Binary to Hexadecimal
Group bits into sets of 4, starting from the binary point (left for integer, right for fraction), padding with zeros where needed.
Grouping
- Integer part: $1011$ (already 4 bits)
- Fractional part: $110 \rightarrow 1100$ (pad right with one zero)
$$\underbrace{1011}{\text{integer}} . \underbrace{1100}{\text{fraction}}$$
Convert each group
Binary Group Decimal Hex Digit $1011$ $11$ $B$ $1100$ $12$ $C$ Result
$$\boxed{(1011.110)2 = (B.C){16}}$$
Summary
From To Result $1011.110_2$ Decimal $11.75_{10}$ $1011.110_2$ Hexadecimal $B.C_{16}$ - 55 marksNumericalBinary decimal octal hexadecimal conversioHideAnswer
Convert 51966.57 decimal number system into octal number system and hexadecimal number system. [5]
- Decimal number: $51966.57$ - Integer part: $51966$ - Fractional part: $0.57$ - Target bases: Octal (8) and Hexadecimal (16) --- Division Quotient Remainder ------------------------------- $51966 \div 8$ 6495 6 $6495 \div 8$ 811 7
- 65 marksNumericalBinary subtraction using complementsHideAnswer
Subtract $(111000.110)_2 - (110100.101)_2$ using both 2's and 1's complement. [5]
- Minuend $A = (111000.110)2$ - Subtrahend $B = (110100.101)2$ - Format: 6 integer bits, 3 fractional bits. --- - $A = 111000.1102 = 56 + 0.75 = 56.75$ - $B = 110100.1012 = 52 + 0.625 = 52.625$ -
- 75 marksBoolean theorems and De Morgan's lawsHideAnswer
State and prove De-Morgan's Theorems. [5]
De-Morgan's Theorems are two fundamental theorems in Boolean algebra: Theorem 1: $$\overline{A + B} = \overline{A} \cdot \overline{B}$$ "The complement of a sum equals the product of the complements." Theorem 2: $$\overline{A \cdot B} = ...
- 85 marksHalf subtractor and full subtractor designHideAnswer
Define Half-subtractor with truth table and logic diagram. [5]
A half-subtractor is a combinational logic circuit that performs subtraction of two single-bit binary numbers. It produces two outputs: the Difference (D) and the Borrow (B). - It subtracts the subtrahend (B) from the minuend (A) - It do...
- 95 marksMultiplexer implementation using smaller mHideAnswer
What is decoder? Implement 8 x 1 MUX using 4 x 1 MUX. [5]
--- A decoder is a combinational logic circuit that converts binary information from n input lines to a maximum of 2ⁿ unique output lines. - It "decodes" a binary code into individual signals. - For each input combination, exactly one ou...
- 105 marksSR latch and clocked RS flip-flopHideAnswer
What is clocked RS flip-flop? Explain with logic diagram and characteristic table. [5]
A clocked RS flip-flop (also called a synchronous RS flip-flop or gated SR latch) is a sequential logic circuit that has an additional clock (CLK) input which controls when the flip-flop responds to its S (Set) and R (Reset) inputs. The ...
- 115 marksCounter design using flip-flopsHideAnswer
Design Mod-3 synchronous counter. [5]
A Mod-3 counter counts in the sequence: 0 → 1 → 2 → 0 → 1 → 2 → ... It requires 2 flip-flops (since 2^2 = 4 ≥ 3) and uses JK flip-flops (standard design approach). --- Present State Next State :---::---: Q1 Q0 Q1+ Q0+ 0 0 0 1 0 1 1 0 1 0...
- 125 marksParallel-in parallel-out shift registerHideAnswer
Draw a Parallel-In Parallel-Out Shift register and explain it. [5]
A Parallel-In Parallel-Out (PIPO) shift register is a type of shift register in which all data bits are loaded simultaneously (in parallel) into the register and all bits are also available at the output simultaneously (in parallel). It ...
- 135 marksBinary parallel adderHideAnswer
Write short notes on Binary parallel adder Write short notes on Jonson counter. [2.5+2.5]
--- A binary parallel adder is a combinational circuit that adds two binary numbers simultaneously (in parallel) by connecting multiple Full Adders (FA) in cascade. - To add two n-bit binary numbers, n full adders are connected in series...