BCD to Excess-3 Code Converter

Definition of BCD Code

BCD (Binary Coded Decimal) is a binary encoding of decimal digits where each decimal digit (0-9) is represented by its 4-bit binary equivalent. Only 10 out of 16 possible 4-bit combinations (0000 to 1001) are valid; the remaining six (1010 to 1111) are invalid/don't-care states.

Definition of Excess-3 Code

Excess-3 (XS-3) is a non-weighted, self-complementing code obtained by adding 3 (0011) to each BCD digit.

Truth Table: BCD to Excess-3

Let BCD inputs be A, B, C, D (A = MSB, D = LSB) Let Excess-3 outputs be W, X, Y, Z (W = MSB, Z = LSB)

(X = don't care)

K-Map Simplification

Output W (minterms: 5,6,7,8,9 + don't cares 10-15)

        CD
AB    00  01  11  10
00  |  0 | 0 | 0 | 0 |
01  |  0 | 1 | 1 | 1 |
11  |  X | X | X | X |
10  |  1 | 1 | X | X |

W = A + BC + BD

Output X (minterms: 1,2,3,4,9 + don't cares 10-15)

        CD
AB    00  01  11  10
00  |  0 | 1 | 1 | 1 |
01  |  1 | 0 | 0 | 0 |
11  |  X | X | X | X |
10  |  0 | 1 | X | X |

X = B'C + B'D + BC'D'

(Simplified: X = BC'D' + B'C + B'D)

Output Y (minterms: 0,3,4,7,8 + don't cares 10-15)

        CD
AB    00  01  11  10
00  |  1 | 0 | 1 | 0 |
01  |  1 | 0 | 1 | 0 |
11  |  X | X | X | X |
10  |  1 | 0 | X | X |

Y = 1 at minterms 0, 3, 4, 7 and 8. On the map those cells fill the columns CD = 00 and CD = 11 for every value of AB, so the two groups are C'D' and CD, and the don't-care row AB = 11 is absorbed into them.

Y = CD + C'D'

(Y = C XNOR D = CD + C'D')

Output Z (minterms: 0,2,4,6,8 + don't cares 10-15)

        CD
AB    00  01  11  10
00  |  1 | 0 | 0 | 1 |
01  |  1 | 0 | 0 | 1 |
11  |  X | X | X | X |
10  |  1 | 0 | X | X |

Z = D'

Simplified Boolean Expressions

Logic Diagram

Inputs: A, B, C, D, with inverters supplying B', C' and D'

W = A + BC + BD
  B ---+--[AND]--- BC ---+
  C ---+                 |
  B ---+--[AND]--- BD ---+--[OR]--- W
  D ---+                 |
  A ---------------------+

X = B'C + B'D + BC'D'
  B' --+--[AND]--- B'C ---+
  C ---+                  |
  B' --+--[AND]--- B'D ---+--[OR]--- X
  D ---+                  |
  B ---+                  |
  C' --+--[AND]-- BC'D' --+
  D' --+

Y = CD + C'D'
  C ---+--[AND]--- CD ----+
  D ---+                  +--[OR]--- Y
  C' --+--[AND]--- C'D' --+
  D' --+

Z = D'
  D -------[NOT]--------- Z

Only two-level AND-OR logic is needed for each output, and the inverters that produce B', C' and D' are shared across all four output networks. Y is the XNOR of C and D, so a single XNOR gate can replace its two AND gates and the OR gate.

Combinational Logic Circuit and 1's Complement Design

Definition of Combinational Logic Circuit (2 marks)

A combinational logic circuit is a digital circuit in which the output at any instant of time depends only on the present input values and not on any previous inputs or outputs. There is no memory element involved; the circuit has no feedback path.

Key characteristics:

• Output is a pure function of current inputs only
• No clock signal or storage elements (flip-flops) are used
• Examples: Adder, Subtractor, Multiplexer, Encoder, Decoder

General model: n input variables produce m output variables through a network of logic gates.

Design of 1's Complement Combinational Circuit (8 marks)

Step 1: Problem Statement

• Input: A 4-bit binary number: A, B, C, D (where A is MSB, D is LSB)
• Output: 1's complement of the input: W, X, Y, Z

The 1's complement of a binary number is obtained by inverting (complementing) each bit individually.

Step 2: Truth Table

Step 3: Boolean Expressions

From the truth table, the output functions are simply:

$$W = A'$$ $$X = B'$$ $$Y = C'$$ $$Z = D'$$

Each output is the complement (NOT) of the corresponding input bit.

Step 4: Logic Diagram

The circuit requires four NOT gates (inverters), one for each input bit:

A ----[NOT]---- W (A')

B ----[NOT]---- X (B')

C ----[NOT]---- Y (C')

D ----[NOT]---- Z (D')

Circuit Diagram:

        +-------+
A ----->|  NOT  |-----> W = A'
        +-------+

        +-------+
B ----->|  NOT  |-----> X = B'
        +-------+

        +-------+
C ----->|  NOT  |-----> Y = C'
        +-------+

        +-------+
D ----->|  NOT  |-----> Z = D'
        +-------+

Step 5: Verification with Example

Example: Input = 1010 (decimal 10)

Output = 0101 which is indeed the 1's complement of 1010. ✓

Summary

Conclusion: The 1's complement of a 4-bit number is the simplest combinational circuit, requiring only four inverters, since each output bit is the logical complement of the corresponding input bit.

Parallel (Synchronous) Counter and MOD-12 Design

Definition of Parallel (Synchronous) Counter

A parallel counter (also called a synchronous counter) is a sequential digital circuit in which all flip-flops receive the clock pulse simultaneously. Unlike ripple (asynchronous) counters where each flip-flop triggers the next, in a synchronous counter the clock is applied in parallel to all flip-flops at the same time.

Key features:

• All flip-flops are clocked simultaneously
• No propagation delay accumulation (faster operation)
• Uses combinational logic (AND gates) to control flip-flop inputs
• Suitable for high-speed applications

MOD-12 Synchronous Up Counter Design

A MOD-12 counter counts from 0 to 11 (0000 to 1011 in binary) and then resets to 0. It requires 4 flip-flops (since 2^4 = 16 > 12).

Step 1: State Diagram

  0000 → 0001 → 0010 → 0011 → 0100 → 0101
    ↑                                      ↓
  1011 ← 1010 ← 1001 ← 1000 ← 0111 ← 0110

States: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 → back to 0

Step 2: State Table

We use JK Flip-Flops (Q3 = MSB, Q0 = LSB).

Step 3: JK Flip-Flop Excitation Table

Recall JK excitation:

Step 4: JK Input Table

States 1100 to 1111 never occur, so their entries are treated as don't-care conditions when the maps are simplified.

Simplified Flip-Flop Input Equations

Reading each column of the input table against the present state gives:

$$J_0 = K_0 = 1$$

$$J_1 = K_1 = Q_0$$

$$J_2 = \overline{Q_3} \cdot Q_1 \cdot Q_0 \qquad K_2 = Q_1 \cdot Q_0$$

$$J_3 = Q_2 \cdot Q_1 \cdot Q_0 \qquad K_3 = Q_1 \cdot Q_0$$

The least significant stage toggles on every pulse, so its inputs are tied to logic 1. Q1 toggles whenever Q0 is high. Q2 is set only at state 0011 and cleared only at state 0111, and the factor Q̄3 is essential: without it the counter would set Q2 while leaving state 1011 and would run to MOD-16. Q3 is set on leaving 0111 and cleared on leaving 1011, which is what folds the count back to zero after 11 and makes the modulus 12.

Logic Circuit

   +---+                                                     
   | 1 |----> J0, K0
   +---+
                Q0 -------------------> J1, K1

                Q1 ---+
                      +--[AND]--+------> K2  and  K3
                Q0 ---+         |
                                +--[AND with Q3']--> J2
                                |
                                +--[AND with Q2 ]--> J3

        +-------+   +-------+   +-------+   +-------+
   J0 ->|       |   |       |   |       |   |       |
        |  FF0  |   |  FF1  |   |  FF2  |   |  FF3  |
   K0 ->|       |   |       |   |       |   |       |
        +---+---+   +---+---+   +---+---+   +---+---+
            |           |           |           |
            Q0          Q1          Q2          Q3
            |           |           |           |
   CLK -----+-----------+-----------+-----------+
            (one common clock to all four flip-flops)

All four flip-flops share one clock line, and only two AND gates plus one inverter are needed to build the input logic, since the term Q₁·Q₀ is reused by K₂ and K₃.

Timing Sequence

Timing Diagram

Pulse     1    2    3    4    5    6    7    8    9   10   11   12
        __   __   __   __   __   __   __   __   __   __   __   __
CLK   _|  |_|  |_|  |_|  |_|  |_|  |_|  |_|  |_|  |_|  |_|  |_|  |_

Q0    ‾‾‾‾‾_____‾‾‾‾‾_____‾‾‾‾‾_____‾‾‾‾‾_____‾‾‾‾‾_____‾‾‾‾‾_____

Q1    _____‾‾‾‾‾‾‾‾‾‾__________‾‾‾‾‾‾‾‾‾‾__________‾‾‾‾‾‾‾‾‾‾_____

Q2    _______________‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾_______________________

Q3    _______________________________________‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾_____

Q₀ divides the clock by two, Q₁ by four and Q₂ by eight for as long as the count is below 8, while Q₃ stays high through counts 8 to 11 and falls on the twelfth pulse. The Q₃ waveform therefore has a period of twelve clock pulses, which confirms the modulus.

Conclusion

A parallel counter clocks all its flip-flops together, so its maximum speed is set by one flip-flop delay plus one gate delay rather than by the sum of the delays in the chain. The MOD-12 design above uses four JK flip-flops with $J_0 = K_0 = 1$, $J_1 = K_1 = Q_0$, $J_2 = \overline{Q_3}Q_1Q_0$, $K_2 = Q_1Q_0$, $J_3 = Q_2Q_1Q_0$ and $K_3 = Q_1Q_0$, which produces the repeating sequence 0 to 11 and returns to 0000 on the twelfth clock pulse.