Drawbacks of Clocked RS Flip Flop and JK Flip Flop

Drawbacks of Clocked RS Flip Flop

The clocked (synchronous) RS flip flop has the following major drawbacks:

1. Forbidden/Invalid State (S=1, R=1): When both inputs S and R are simultaneously HIGH (S=1, R=1), the output becomes indeterminate or unpredictable (Q and Q' both try to become 1, which is a contradiction). This is the most critical limitation.

2. Restricted Input Combinations: The designer must always ensure S and R are never both 1 at the same time, which adds complexity to circuit design and requires extra gating logic.

3. No Toggling Capability: The clocked RS flip flop cannot toggle its output (switch from current state to its complement) with a single input condition. This limits its use in counters and frequency dividers.

4. Incomplete Utilization of Input States: Out of four possible input combinations (00, 01, 10, 11), one combination (11) is forbidden, meaning the flip flop does not make full use of all input states.

5. Unreliable Behavior in Asynchronous Environments: If S and R both go HIGH and then LOW simultaneously (race condition), the final state of the flip flop is unpredictable.

The JK flip flop was designed specifically to overcome these drawbacks.

JK Flip Flop

Introduction

The JK flip flop is an improved and universal flip flop that eliminates the forbidden state of the RS flip flop. The inputs are renamed J (analogous to S, Set) and K (analogous to R, Reset). The key improvement is that when J=1 and K=1, the output toggles (complements itself) instead of going to an invalid state.

Circuit Diagram

The JK flip flop is typically constructed using a clocked RS flip flop (NAND gate based) with feedback connections from the outputs back to the input gates.

        +-------+
J ------|       |
        | NAND  |----S-----+-------+
CLK ----|       |          |  SR   |----Q
        +-------+          | F/F   |
                           |       |----Q'
        +-------+          +-------+
K ------|       |
        | NAND  |----R
Q' -----|       |
        +-------+
  (Q feeds back to K-gate, Q' feeds back to J-gate)

Key Feature: Q is fed back to the K-input NAND gate, and Q' is fed back to the J-input NAND gate. This feedback resolves the ambiguity when J=K=1.

A more standard representation:

         ___________
        |           |
  J ----|  J     Q  |---- Q
        |           |
CLK ----|> CLK      |
        |           |
  K ----|  K     Q' |---- Q'
        |___________|

Operation of JK Flip Flop

The operation is governed by the clock pulse (CP). The flip flop responds to inputs only at the active clock edge.

Explanation of each case:

• J=0, K=0: Both NAND gates are disabled. Output remains unchanged. Memory state is retained.
• J=0, K=1: The flip flop is reset. Output Q goes to 0 regardless of current state.
• J=1, K=0: The flip flop is set. Output Q goes to 1 regardless of current state.
• J=1, K=1: The feedback connections ensure the flip flop toggles. If Q=0, it becomes 1; if Q=1, it becomes 0. This is the key improvement over RS flip flop.

Characteristic Table

The characteristic table shows the next state Q(t+1) as a function of current inputs J, K and current state Q(t):

Characteristic Equation

The characteristic equation (next state equation) is derived from the characteristic table using a Karnaugh Map:

K-Map for Q(t+1):

Variables: Q(t), J, K

         JK
Q(t) | 00 | 01 | 11 | 10
-----|----|----|----|----|
  0  |  0 |  0 |  1 |  1 |
  1  |  1 |  0 |  0 |  1 |

Grouping:

• Group 1: J=1, Q(t)=0 and J=1, Q(t)=1 (when K=0) --> J . Q' ... (cells with J=1, K=0)
• Group 2: Q(t)=1, K=0