i. Draw the timing diagram for a instruction cycle and explain. ii. Give a note on subroutine.

(i) Timing diagram of the instruction cycle

The fetch part takes three clock pulses (T0 to T2). The decode part takes one more (T3). The execute part follows. The register transfers are given below.

$$T_0:; AR \leftarrow PC$$

$$T_1:; IR \leftarrow M[AR],; PC \leftarrow PC + 1$$

$$T_2:; D_0,\dots,D_7 \leftarrow \text{decode } IR(12\text{-}14),; AR \leftarrow IR(0\text{-}11),; I \leftarrow IR(15)$$

At T0 the address of the next instruction goes from the program counter (PC) to the address register (AR). At T1 the instruction is read from memory into the instruction register (IR), and PC moves on to the next address. At T2 the opcode is decoded and the address field is saved in AR. The mode bit I tells if the address is direct or indirect.

In the next clock pulse, if the instruction is indirect, the effective address is read as $AR \leftarrow M[AR]$ at T3. Then the execute phase starts with the timing signals T4, T5, T6 and so on. For example, for an ADD instruction the steps are:

$$T_4:; DR \leftarrow M[AR]$$

$$T_5:; AC \leftarrow AC + DR,; SC \leftarrow 0$$

Setting the sequence counter SC to zero at the end starts the next fetch at T0. The sequence counter (SC) is the small counter that produces the timing signals T0, T1, T2 and so on.

(ii) Subroutine

A subroutine is a group of instructions that does one job and can be used many times from different places in a program. It saves memory because the code is written once. The main program uses a CALL instruction to run it. The CALL stores the return address, which is the address of the next instruction, usually on the stack. Then it loads the subroutine address into PC. At the end, a RETURN instruction pops the saved address back into PC. The main program then continues from where it left off.

$$SP \leftarrow SP - 1,; M[SP] \leftarrow PC,; PC \leftarrow \text{subroutine address}$$

Because the return address is on a stack, subroutines can call other subroutines, and even themselves (recursion).

Interrupt and sub cycles. Before each fetch, the CPU also checks if an interrupt is pending. If the interrupt flip-flop is set, the CPU saves the return address, usually in memory location 0, and jumps to the interrupt service routine. So the full cycle is fetch, decode, read the effective address if indirect, execute, and then the interrupt check. Each of these is a sub cycle, and each is driven by the timing signals from the sequence counter.

Why the timing diagram matters. It shows exactly in which clock pulse each register is loaded. The control unit uses these timing signals together with the decoded opcode to produce the control signals. Memory reads and writes also fit inside these pulses, so the whole machine stays in step with one clock.