2024 25 3a

Computer Organization and Architecture2024-257 marksProgram Control, Reduced Instruction Set Computer, Pipelinin

Provide a detailed overview of processor organization, covering topics such as instruction fetch, decode, execute cycles, pipelining, and parallel processing techniques?

Provide a detailed overview of processor organization, covering topics such as instruction fetch, decode, execute cycles, pipelining, and parallel processing techniques?

Quick answer

A processor has a datapath and a control unit. The datapath holds the registers, the ALU and the buses. The control unit gives the signals. The main registers are the program counter (PC), instruction register (IR), address register (AR), data register (DR), accumulator (AC) and general registers.

Processor organization

Instruction fetch, decode and execute

The CPU repeats a basic cycle for every instruction.

  • Fetch: the address in PC goes to AR. The instruction is read into IR, and PC is incremented.
  • Decode: the control unit decodes the opcode and finds the addressing mode.
  • Execute: the ALU or other unit does the operation. The operands are read from registers or memory, and the result is stored.

$$AR \leftarrow PC,\quad IR \leftarrow M[AR],\quad PC \leftarrow PC + 1$$

The control unit times these steps with a sequence counter, and it may check for interrupts at the end.

Pipelining

Pipelining overlaps the cycles of different instructions. The work is split into stages such as fetch, decode, execute, memory and write back. While one instruction is executed, the next is decoded, and a third is fetched. After the pipeline fills, one instruction finishes in every clock cycle. For $k$ stages and $n$ instructions:

$$S = \frac{nk}{k + n - 1}$$

Hazards (structural, data and control) can slow it, and they are cured by stalls, forwarding and branch prediction.

Parallel processing techniques

Parallel processing means doing many operations at the same time to increase speed. It can be done at several levels:

  • Instruction-level: pipelining and superscalar processors that issue many instructions in a cycle.
  • Data-level: vector and array processors, and GPUs, apply one instruction to many data items.
  • Thread and processor-level: multicore and multiprocessor systems run different tasks or threads together.

In Flynn's classification there are four types: SISD, SIMD, MISD and MIMD. A normal single core CPU is SISD, a vector unit is SIMD, and a multicore machine is MIMD.

Control

Control can be hardwired for speed or microprogrammed for flexibility. In all cases the control unit decides what happens in each clock pulse, and the processor organization decides how fast the work is done.

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