Explain the concept of look-ahead carry adders in digital arithmetic circuits. Compare and contrast their performance with conventional ripple carry adders, highlighting advantages and disadvantages?
Explain the concept of look-ahead carry adders in digital arithmetic circuits. Compare and contrast their performance with conventional ripple carry adders, highlighting advantages and disadvantages?
Quick answer
A look-ahead carry adder finds all carry bits at the same time, directly from the inputs. For each bit $i$ it uses the generate signal $G_i = A_iB_i$ and the propagate signal $P_i = A_i \oplus B_i$.
A look-ahead carry adder finds all carry bits at the same time, directly from the inputs. For each bit $i$ it uses the generate signal $G_i = A_iB_i$ and the propagate signal $P_i = A_i \oplus B_i$. Then:
$$S_i = P_i \oplus C_i \qquad C_{i+1} = G_i + P_iC_i$$
If we replace each carry by the one before it, every carry depends only on $G$, $P$ and $C_0$:
$$C_1 = G_0 + P_0C_0$$
$$C_2 = G_1 + P_1G_0 + P_1P_0C_0$$
$$C_3 = G_2 + P_2G_1 + P_2P_1G_0 + P_2P_1P_0C_0$$
Each of these is a two-level AND-OR circuit. So all carries are ready after two gate delays, and they do not wait for each other.
A ripple carry adder is a chain of full adders. The carry out of each stage is the carry in of the next one. The last sum bit is ready only after the carry has passed through all $n$ stages. For a 4-bit adder with two gate delays per stage, this takes about 8 gate delays.
Comparison
| Point | Ripple carry adder | Look-ahead carry adder |
|---|---|---|
| Carry calculation | one stage after another | all together |
| Delay | grows with $n$ (about $2n$ gate delays) | almost constant, about 4 gate delays for 4 bits |
| Hardware | very simple, $n$ full adders | more gates and a look-ahead unit |
| Gate fan-in | 2 or 3 inputs | grows with $n$ |
| Cost and size | low | high |
| Use | small, cheap circuits | fast processors |
Advantages of the look-ahead adder: it is much faster, and the speed is nearly independent of word length for one block.
Disadvantages: it needs many more gates, so it costs more and uses more power. For long words the AND and OR gates need too many inputs, so in practice the adder is built from 4-bit blocks joined by a second level of look-ahead.
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