Explain in detail the principle of carry look ahead adder and design 4-bit CLA adder.

For each bit position $i$ we define two signals. The generate signal $G_i = A_i B_i$ says that this stage makes a carry on its own. The propagate signal $P_i = A_i \oplus B_i$ says that this stage passes an incoming carry forward. The sum and the next carry are then:

$$S_i = P_i \oplus C_i$$

$$C_{i+1} = G_i + P_i C_i$$

If we keep replacing the earlier carry in this equation, every carry depends only on $G$, $P$ and $C_0$:

$$C_1 = G_0 + P_0 C_0$$

$$C_2 = G_1 + P_1 G_0 + P_1 P_0 C_0$$

$$C_3 = G_2 + P_2 G_1 + P_2 P_1 G_0 + P_2 P_1 P_0 C_0$$

$$C_4 = G_3 + P_3 G_2 + P_3 P_2 G_1 + P_3 P_2 P_1 G_0 + P_3 P_2 P_1 P_0 C_0$$

Each of these is a two-level AND-OR circuit. So all four carries appear after the same two gate delays, no matter which bit it is. The 4-bit CLA is built from these parts: four half-adder style gates that make $P_i$ and $G_i$, one look-ahead logic block that holds the four equations above, and four XOR gates that make the sums.

 A3B3  A2B2  A1B1  A0B0
  |     |     |     |
 [P,G] [P,G] [P,G] [P,G]   (AND gate gives G, XOR gives P)
  |     |     |     |
 +-----------------------+
 |  look-ahead carry     |<-- C0
 |  logic (C1, C2, C3,C4)|--> C4
 +-----------------------+
  |C3   |C2   |C1   |C0
 [XOR] [XOR] [XOR] [XOR]    (S = P xor C)
  |     |     |     |
  S3    S2    S1    S0

Example. Add $A = 1011$ and $B = 0110$ with $C_0 = 0$. The bitwise values, from bit 0 to bit 3, are:

Using the look-ahead equations with $C_0 = 0$:

$$C_1 = G_0 + P_0 C_0 = 0$$

$$C_2 = G_1 + P_1 G_0 + P_1 P_0 C_0 = 1$$

$$C_3 = G_2 + P_2 G_1 + P_2 P_1 G_0 + P_2 P_1 P_0 C_0 = 0 + 1 + 0 + 0 = 1$$

$$C_4 = G_3 + P_3 G_2 + P_3 P_2 G_1 + \dots = 0 + 0 + 1 + 0 + 0 = 1$$

The sum bits are $S_i = P_i \oplus C_i$. This gives $S_0 = 1 \oplus 0 = 1$, $S_1 = 0 \oplus 0 = 0$, $S_2 = 1 \oplus 1 = 0$ and $S_3 = 1 \oplus 1 = 0$. With the final carry $C_4 = 1$, the result is $10001$. Therefore $11 + 6 = 17$, which matches.

Speed. Making $P$ and $G$ takes one gate delay, the look-ahead block takes two, and the last XOR takes one. The total is about 4 gate delays for any $n$ that fits in one block. A 4-bit ripple adder needs about 8. The cost is more gates, and the AND-OR gates need more inputs as $n$ grows, so large adders use several 4-bit CLA blocks joined in groups.