Draw the flowchart for instruction cycle with neat diagram and explain.

Flowchart

        +------------------+
        |  START (PC set)  |
        +--------+---------+
                 v
        +------------------+
        | FETCH: AR <- PC  |
        | IR <- M[AR]      |
        | PC <- PC + 1     |
        +--------+---------+
                 v
        +------------------+
        | DECODE opcode,   |
        | read mode bit I  |
        +--------+---------+
                 v
          < indirect? >--yes--> AR <- M[AR]
                 | no                 |
                 +<-------------------+
                 v
        +------------------+
        |     EXECUTE      |
        +--------+---------+
                 v
          < interrupt? >--yes--> save PC, go to ISR
                 | no
                 +---------> back to FETCH

Explanation

The cycle has four main phases.

Fetch. The address in the program counter (PC) goes to the address register (AR). The memory word at that address is read into the instruction register (IR). Then PC is increased by one so that it points to the next instruction. This is written as follows.

$$AR \leftarrow PC$$

$$IR \leftarrow M[AR],; PC \leftarrow PC + 1$$

Decode. The control unit looks at the opcode bits of IR and finds which operation is needed. A decoder turns the three opcode bits into one of eight lines. The mode bit I tells whether the operand address is direct or indirect.

Read the effective address. If the instruction is indirect, the address field only points to a memory word that holds the real operand address. So the CPU reads that word:

$$AR \leftarrow M[AR]$$

For a direct instruction, nothing more is needed here.

Execute. The operation is carried out. A memory-reference instruction such as ADD reads the operand into the data register DR and adds it to the accumulator AC. A register-reference instruction such as CLA clears AC. A branch instruction loads a new address into PC. An input-output instruction moves data to or from a device.

Interrupt check. After the execute phase, the CPU checks if an interrupt request has come. If yes, it saves the contents of PC (the return address), and starts the interrupt service routine. When the routine finishes, the return address is restored, and the program goes on. If no interrupt is pending, control goes back to the fetch phase for the next instruction.

All these steps are timed by the sequence counter, which generates the pulses T0, T1, T2 and so on. At the end of each instruction the counter is cleared, so the next fetch starts again at T0.

A worked example. Suppose PC holds 300 and the word at address 300 is the instruction ADD 500, with the mode bit I equal to 0. In the fetch phase, AR gets 300, IR gets the word from location 300, and PC becomes 301. In the decode phase, the decoder finds that it is an ADD, and the address field gives 500. As the instruction is direct, there is no indirect read. In the execute phase, the word at address 500 is read into DR, and AC is replaced by $AC + DR$. The sequence counter is cleared, and the next instruction at 301 is fetched.

Why the cycle matters. Every program, however large, runs only by repeating this loop. The speed of a computer in a large part depends on how fast the loop runs. Pipelining overlaps the loops of different instructions to make it faster.