2019 20 6b

Computer Organization and Architecture2019-2010 marksNumericalsemiconductor RAM memories, 2D & 2 1/2D memory organization

RAM chip 4096 x 8 bits has two enable lines. How many pins are needed for the integrated circuits package? Draw a block diagram and label all input and outputs of the RAM. What is main feature of random-access memory?

RAM chip 4096 x 8 bits has two enable lines. How many pins are needed for the integrated circuits package? Draw a block diagram and label all input and outputs of the RAM. What is main feature of random-access memory?

The chip stores $4096 \times 8$ bits, that is 4096 words of 8 bits each, or 4 KB.

Pins needed

Since $2^{12} = 4096$, the chip needs 12 address lines. It needs 8 data lines, which are bidirectional. There are 2 enable (chip select) lines and 1 read/write control line. These make

$$12 + 8 + 2 + 1 = 23$$

signal pins. Two more pins are needed for the power supply and ground, so the package has 25 pins in all.

Block diagram and labels

                 +----------------------+
  Address  12 -->|                      |
                 |    RAM 4096 x 8      |<--> Data (8)
  CS1 ---------->|                      |
  CS2 ---------->|                      |
  R/W ---------->|                      |
                 +----------------------+
                   Vcc, GND (power pins)

Inputs are the 12 address lines, the two enables CS1 and CS2, and the read/write line R/W. The 8 data lines are both input and output. The chip works only when both enables are active. Then R/W = 1 reads a word onto the data lines, and R/W = 0 writes the data lines into the addressed word. If the chip is not enabled, the data lines are in the high impedance state.

CS1CS2R/WOperation
inactiveanyanyno operation (high impedance)
anyinactiveanyno operation (high impedance)
activeactive1read
activeactive0write

Inside the chip

The 12 address bits go to an internal decoder. The decoder selects one of the 4096 words in the cell array. The selected 8 cells are connected to the data lines through tri-state buffers. These buffers are on only when the chip is enabled, so many chips can share one data bus without clashing.

The total size follows from the pins:

$$2^{12} \times 8 = 4096 \times 8 = 32768 \text{ bits}$$

Two enable lines are given so that a larger memory can be built easily. One enable can come from the high address bits through a decoder, and the other can come from a control signal such as the memory-request line. For instance, if the chip is placed at the start of the address space, its address range is $\text{0x000}$ to $\text{0xFFF}$.

The same rule gives the pin count for any RAM chip. Address pins equal $\log_2$ of the number of words, data pins equal the word width, and a few control pins are added. A larger chip such as $8192 \times 8$ would need one more address pin, so 13, while its data pins would stay at 8.

Main feature of RAM

In a random-access memory, every location can be reached in the same time, whatever its position in the memory. The time does not depend on the address used. A RAM can be both read and written, and it is volatile, so it loses its data when power is switched off.

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