Explain the memory hierarchy with diagram. A memory chip has a capacity of 64K x 8. i. Find the number of address lines required. ii. How many such chips are needed to design a 256K x 16 memory system?

Memory hierarchy

A computer uses several kinds of memory, arranged in levels. The levels near the CPU are small, fast and costly. The levels far from the CPU are large, slow and cheap.

The levels are CPU registers, cache, main memory, magnetic disk, and tape or optical disk. Going down the hierarchy, the size and access time grow and the cost per bit falls. The hierarchy works because of locality of reference: programs reuse recent data and use data near it. So most accesses are served by the fast upper levels, and the system looks like a memory that is as fast as the cache and as large as the disk. Data moves between the cache and main memory in blocks, and between main memory and disk in pages.

Numerical

The chip has a capacity of $64\text{K} \times 8$. That is 65536 words of 8 bits each.

(i) The number of address lines is

$$\log_2 65536 = 16$$

So 16 address lines are needed.

(ii) The required memory is $256\text{K} \times 16$. The number of chips is

$$\frac{256\text{K} \times 16}{64\text{K} \times 8} = 4 \times 2 = 8$$

So 8 chips are needed.

The word width is 16 bits and a chip gives only 8 bits, so 2 chips are put side by side to make a 16-bit word. The memory has 256K words and a chip has 64K words, so 4 such rows of chips are needed to get 256K words. The chips form 4 rows and 2 columns.

The system has $256\text{K} = 2^{18}$ words, so it has 18 address lines. The lower 16 lines go to all chips in parallel. The upper 2 lines go to a $2 \times 4$ decoder. Each output of the decoder enables one row of 2 chips. Only that row works at a time. The two chips of the row give the upper and lower bytes of the 16-bit word.

 A17 A16 --> [2x4 decoder] -> CS of row 0..3
 A15..A0 --> all 8 chips
 Row k : [64Kx8 chip] [64Kx8 chip] -> D15..D8, D7..D0