Discuss the process of signed operand multiplication in digital arithmetic circuits?

Signed operand multiplication means multiplying numbers that may be positive or negative. There are three common ways.

Sign-magnitude method. The sign and the magnitude are handled separately. The sign of the product is the XOR of the two signs. The magnitudes are multiplied by the shift-and-add method. For example, $5 \times (-3)$: the magnitudes are $101$ and $011$. Adding the shifted copies gives:

$$101 + 1010 = 1111 = 15$$

The signs are $0 \oplus 1 = 1$, so the product is negative. Therefore $5 \times (-3) = -15$.

2's complement method. The numbers are kept in 2's complement form. The multiplicand is first sign-extended to the length of the product. If the multiplier is negative, its leftmost bit has the negative weight $-2^{n-1}$. So the partial product made by that bit is subtracted and not added. For $5 \times (-3)$, the multiplier is $1101$, and the multiplicand is $0101$. The bit weights are $-8, +4, 0, +1$, so:

$$5 \times (-3) = 5 \times 1 + 5 \times 4 - 5 \times 8 = 5 + 20 - 40 = -15$$

This avoids converting the multiplier to a positive number.

Booth's algorithm. It handles signed multipliers in a single uniform procedure. Each cycle checks the pair $Q_0Q_{-1}$. The pair $10$ subtracts the multiplicand, the pair $01$ adds it, and the pairs $00$ and $11$ do nothing. After each cycle $A$, $Q$ and $Q_{-1}$ are shifted right with the sign of $A$ kept. After $n$ cycles, the $2n$-bit product is in $AQ$. It needs no separate sign logic, and it skips runs of equal bits.

Comparison

In all methods the product of two $n$-bit numbers needs $2n$ bits. Hardware multipliers usually use Booth's algorithm or its improved form, because it is simple and works for both signs.