Discuss 2 D RAM and 2.5D RAM with suitable diagram.

2D organization

In 2D organization the cells are arranged as a two-dimensional array of words. Each row is one word, and each word has its own word line. A single decoder takes all $n$ address bits and activates exactly one of the $2^n$ word lines. All bits of that word are then read or written through the bit lines.

 Address (n bits) --> [ n to 2^n decoder ]
                        | word line 0 ---> [ word 0 ]
                        | word line 1 ---> [ word 1 ]
                        | ...
                        | word line 2^n-1 > [ word 2^n-1 ]
                                               |  |  |
                                         bit lines to R/W circuit

The decoder is a big circuit. For a $64\text{K} \times 1$ memory, $n = 16$, so the decoder has $2^{16} = 65536$ output lines and 65536 AND gates. This is costly and slow, and it takes a large area. So 2D organization suits only small memories.

2 1/2D organization

Here the cells are arranged in a square-like array of rows and columns, and the address is split into two halves. A row decoder takes the upper half and selects one row. A column decoder takes the lower half and selects one column through a multiplexer (or a column selector). The cell at the crossing of the chosen row and column is read or written.

 Row address (n/2) --> [ row decoder ] --> row lines
                                              |
                                   +------------------+
                                   |   cell array     |
                                   |  (rows x cols)   |
                                   +------------------+
                                              |
 Col address (n/2) --> [ column decoder / mux ] --> data bit

For the same $64\text{K} \times 1$ memory, the cells form a $256 \times 256$ array. The row decoder has 8 inputs and 256 outputs, and the column decoder also has 256 outputs. The total number of decoder outputs is

$$256 + 256 = 512$$

compared with 65536 in the 2D scheme. The saving is large. The name "2 1/2D" is used because the structure is more than a plain 2D array but not a full 3D one.

Comparison

The 2 1/2D scheme is also easy to refresh, because DRAM can refresh a whole row in one step. This is why modern memory chips use it.

In short, the 2D scheme is easy to understand but wastes area on the decoder, and the 2 1/2D scheme saves that area by splitting the address, which is why large memory chips follow it.