2021 22 4a

Computer Organization and Architecture2021-2210 marksRegister, bus and memory transfer

Draw a diagram of a Bus system in which it uses 3 state buffers and a decoder instead of the multiplexers.

Draw a diagram of a Bus system in which it uses 3 state buffers and a decoder instead of the multiplexers.

Quick answer

A three-state buffer is a gate that has three output states: logic 0, logic 1, and high impedance. In the high-impedance state the output is disconnected, as if the gate were not there. A control input decides this. When the control input is 1, the buffer passes its input to the output. When the control input is 0, the output is in high impedance.

Because a disabled buffer does not affect the line, the outputs of many buffers can be joined to one wire. We only need to make sure that one buffer is enabled at a time. That is how a common bus is formed without multiplexers.

Bus with four registers

Take four registers A, B, C and D of 4 bits each. For every register there is a group of four 3-state buffers, one for each bit. The outputs of the four buffers of the same bit position are tied together to make that bit of the bus. A 2-to-4 decoder produces the enable signals. Its two inputs $S_1S_0$ select the register, and each of its four outputs enables the group of buffers of one register.

 S1 S0 --> [ 2-to-4 DECODER ]
            |   |   |   |
           E_A E_B E_C E_D   (enable of each buffer group)
            |   |   |   |
          [buf][buf][buf][buf]   4 buffers per register
            ^   ^   ^   ^
            A   B   C   D        (registers)
            |   |   |   |
            +---+---+---+--->  4-bit common bus

Working

The decoder makes exactly one of its outputs 1 for each value of $S_1S_0$.

$S_1S_0$Enabled groupRegister on bus
00E_AA
01E_BB
10E_CC
11E_DD

Suppose $S_1S_0 = 01$. Only the buffers of B are enabled. Their outputs show the bit values of B on the bus. The buffers of A, C and D are in high impedance, so they do not affect the bus. The data on the bus can then be loaded into any register whose load input is enabled at the clock pulse.

Care is needed in the design. If two groups of buffers were enabled together, two different values would try to drive the same wire. This is a bus conflict, and it can damage the circuit. The decoder prevents it, because it never enables more than one output at a time.

Comparison with the multiplexer bus

A multiplexer bus needs one multiplexer for every bit. A three-state bus replaces the set of multiplexers by buffers and a single decoder. For 8 registers of 16 bits, the multiplexer method needs sixteen 8-to-1 multiplexers. The buffer method needs 128 buffers and one 3-to-8 decoder.

The three-state method also has an important advantage: the bus can be extended simply by connecting one more set of buffers. It is easy to build in integrated circuits, and it can carry data in both directions. Real computer buses use this idea.

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