Explain in detail multiple bus organization with the help of a diagram.

Three-bus organization of the CPU

The common design has bus A, bus B and bus C. The registers are in a register file with two read ports and one write port. Bus A and bus B carry the two source operands from the register file to the two inputs of the ALU. Bus C carries the ALU result back to the register file.

  +--------------------------------+
  |        Register file R0..Rn    |
  +--+--------------+----------^---+
     |A bus         | B bus    | C bus
     v              v          |
   +---------------------+     |
   |         ALU         |-----+
   +---------------------+

The program counter, the instruction register, the memory address register and the memory data register also connect to these buses, as needed.

Working

In one clock cycle, two registers are read onto bus A and bus B, the ALU adds them, and the result is written to a third register through bus C. For example, ADD R4, R1, R2 with $R4 \leftarrow R1 + R2$ needs only one clock step. In a single bus system, the same instruction needs three steps. First R1 is moved to a temporary register, then R2 is put on the bus and added, and then the result is moved to R4.

Advantages

• Fewer clock cycles per instruction, so the program runs faster.
• Two operands can be read at the same time.
• No temporary registers such as the Y register are needed for ALU inputs.
• It supports pipelining more easily.

Disadvantages

• More wires and more control signals are needed.
• The hardware and the cost are higher.
• The control unit becomes more complex.

Example of the saving

Take the three instructions ADD R4, R1, R2, SUB R5, R4, R3 and MUL R6, R5, R1. On a three-bus CPU each of them needs one data-path step, so three steps in all. On a single bus CPU, each needs about three steps, so nine steps in all. The three-bus design is therefore about three times faster for this short program, although the real gain depends on the program and the instruction mix.

Other multiple bus use

At the system level, there may be separate buses for memory and for I/O, or separate address, data and control buses. Some systems also have a fast local bus for the CPU and the cache, and a slower expansion bus for devices, joined by a bridge. The slow devices then do not delay the fast ones.

So multiple bus organization improves the performance of the processor by allowing parallel transfers, at the price of a higher cost and more complex control.