Explain the design of an Arithmetic and Logic Unit. Describe various arithmetic and logical operations performed by ALU.

        A_i        B_i
         |          |
         |   +------+------+
         |   | logic for B  |<-- S1 S0 (select B, B', 0, 1)
         |   +------+------+
         |          |
      +--+----------+--+
      |   full adder    |<-- C_i
      +--+--------------+--> C_i+1
         |
      +--+------------------+
      | logic gates AND,OR, |<-- S3 S2 (select)
      | XOR, NOT on A_i,B_i |
      +--+------------------+
         |
      [4:1 MUX] --> F_i

The arithmetic part is a parallel adder. A set of gates on the $B$ input decides what the adder sees. They can pass $B$, pass $\overline{B}$, or pass all 0s or all 1s. With the carry input $C_0$, this gives the different operations.

The logic part applies a gate to each bit pair separately. It gives AND, OR, XOR and complement (NOT). No carry moves between the bits.

A multiplexer (MUX) in each slice chooses between the arithmetic result and the logic result, using the select lines. The ALU also gives status flags: carry $C$, sign $S$, zero $Z$ and overflow $V$. Overflow is $V = C_n \oplus C_{n-1}$, the XOR of the last two carries.

Operations performed

• Arithmetic: addition, subtraction, increment, decrement and transfer.
• Logical: AND, OR, XOR, NOT.
• Shift: logical shift and arithmetic shift left or right, and rotate.

The control unit gives the select code that picks the operation. The result goes to a register, and the flags are stored in the status register for conditional branches.