Multiply the following numbers using Array Multiplier technique: A = 1101, B = 1011

An array multiplier makes all the partial products at the same time with AND gates, and adds them with a regular array of adders. Here $A = 1101$ ($13$) is the multiplicand and $B = 1011$ ($11$) is the multiplier.

Each bit of $B$ is ANDed with every bit of $A$. If the multiplier bit is 1, the row is a copy of $A$. If it is 0, the row is all zeros. Each row is shifted one place left from the one above it:

Now the rows are added column by column. In hardware, this is done by full adders and half adders arranged in a grid. The carry of each adder goes to the next column, and the sum goes to the adder in the row below.

$$00001101 + 00011010 = 00100111$$

$$00100111 + 00000000 = 00100111$$

$$00100111 + 01101000 = 10001111$$

Therefore $1101 \times 1011 = 10001111_2$, which is $128 + 8 + 4 + 2 + 1 = 143$. Check: $13 \times 11 = 143$.

Structure. For an $n \times n$ multiplier, the array needs $n^2$ AND gates and about $n(n-1)$ adders. For 4 bits this means 16 AND gates and 12 adders (a mix of full adders and half adders). All partial products are formed in one gate delay. The total delay is the time for a carry and a sum to pass through the array, which grows in proportion to $n$.

Advantages. The design is regular and easy to lay out on a chip. It needs no clock or control unit, since it is purely combinational. It is much faster than the shift-and-add method, which needs $n$ clock cycles.

Disadvantage. The hardware grows as $n^2$, so large multipliers need a lot of area.