Explain in detail the principle of carry look ahead adder and design 4-bit CLA adder.

For each bit $i$ we define two signals. The generate signal $G_i = A_iB_i$ means this stage makes a carry on its own. The propagate signal $P_i = A_i \oplus B_i$ means this stage passes an incoming carry on. Then:

$$S_i = P_i \oplus C_i \qquad C_{i+1} = G_i + P_iC_i$$

Replacing each carry by the equation of the stage before gives the carries of a 4-bit adder in terms of $G$, $P$ and $C_0$ only:

$$C_1 = G_0 + P_0C_0$$

$$C_2 = G_1 + P_1G_0 + P_1P_0C_0$$

$$C_3 = G_2 + P_2G_1 + P_2P_1G_0 + P_2P_1P_0C_0$$

$$C_4 = G_3 + P_3G_2 + P_3P_2G_1 + P_3P_2P_1G_0 + P_3P_2P_1P_0C_0$$

Each carry is a two-level AND-OR circuit. So all four carries are ready after the same two gate delays.

Design of the 4-bit CLA. The circuit has three layers. The first layer has an AND gate and an XOR gate for each bit. They give $G_i$ and $P_i$. The second layer is the look-ahead logic that makes $C_1$ to $C_4$ from the four equations above. The third layer has four XOR gates that give $S_i = P_i \oplus C_i$.

   A3B3   A2B2   A1B1   A0B0
    |      |      |      |
  [AND,XOR] x4  ->  G3..G0, P3..P0
    |      |      |      |
  +--------------------------+
  | look-ahead carry logic   |<-- C0
  | C1  C2  C3  C4           |
  +--------------------------+
    |C3    |C2    |C1    |C0
  [XOR]  [XOR]  [XOR]  [XOR]
    S3     S2     S1     S0

The delay is about 4 gate delays in total (one for $P,G$, two for the carries, one for the XOR). A 4-bit ripple carry adder needs about 8. The price is more gates, and wider AND-OR gates for longer words. So big adders use 4-bit CLA blocks joined together.