A computer uses RAM chips of 1024*1 capacity. i) How many chips are needed & how should their address lines be connected to provide a memory capacity of 1024*8? ii) How many chips are needed to provide a memory capacity of 16 KB?

(i) Memory of 1024 x 8

Each chip stores 1024 words of 1 bit. A word of 8 bits needs 8 bits in parallel, so

$$\text{chips} = \frac{1024 \times 8}{1024 \times 1} = 8$$

The memory has 1024 words, so it needs 10 address lines because $2^{10} = 1024$. All 10 address lines are connected in parallel to every one of the 8 chips. Each chip gives one bit of the word, so the data pin of chip 0 is bit 0, that of chip 1 is bit 1, and so on up to bit 7. The read/write line and the chip select line are also common to all chips. All 8 chips work together as one 8-bit wide memory.

Connection diagram for part (i)

 A9..A0 (10 lines) ---+----+----+--- ... ---+  (to all 8 chips)
 R/W, CS -------------+----+----+--- ... ---+
                      |    |    |           |
                   [chip0][chip1][chip2] .. [chip7]
                      |    |    |           |
                     D0   D1   D2   ...    D7

Here the lines D0 to D7 form the 8-bit data bus of the memory. Because the address lines are shared, a single address selects the same cell position in all 8 chips. The 8 bits read from them together form one memory word. This is called widening the word length. When the memory must be made deeper (more words), more groups are added, and the extra high address lines select one group, as shown below.

(ii) Memory of 16 KB

Take 1 byte as 8 bits. Then 16 KB is $16 \times 1024 = 16384$ words of 8 bits, that is $16384 \times 8 = 131072$ bits. Each chip holds 1024 bits, so

$$\text{chips} = \frac{16384 \times 8}{1024 \times 1} = 128$$

So 128 chips are needed. They form 16 groups of 8 chips, and each group is a $1024 \times 8$ block like the one in part (i).

The memory has 16384 words, so it needs 14 address lines because $2^{14} = 16384$. The lower 10 lines go to all chips in parallel. The upper 4 lines go to a $4 \times 16$ decoder. Each decoder output enables one group of 8 chips. In this way only one group works at a time.

For instance, the address with A13 to A10 equal to 0101 enables group 5. That group holds the words from $5 \times 1024 = 5120$ to $5120 + 1023 = 6143$. The other 15 groups stay idle, and their data outputs are in the high impedance state. This allows all 16 groups to share the same 8 data lines.

In short, adding chips side by side widens the word, and adding chip groups with a decoder increases the number of words.