2021 22 2c

Computer Organization and Architecture2021-2210 marksDivision and logic operations

Explain 2-bit by 2-bit Array multiplier. Draw the flowchart for divide operation of two numbers in signed magnitude form.

Explain 2-bit by 2-bit Array multiplier. Draw the flowchart for divide operation of two numbers in signed magnitude form.

Quick answer

An array multiplier forms all partial products at the same time with AND gates, and then adds them with an array of adders. Let the multiplicand be $A = a_1a_0$ and the multiplier be $B = b_1b_0$. The product $P = p_3p_2p_1p_0$ has 4 bits.

Each partial product bit is one AND gate: $a_0b_0$, $a_1b_0$, $a_0b_1$ and $a_1b_1$. They are arranged like paper multiplication:

Weight$2^3$$2^2$$2^1$$2^0$
Row 1 ($b_0$)$a_1b_0$$a_0b_0$
Row 2 ($b_1$)$a_1b_1$$a_0b_1$

Column $2^0$ has one bit, so $p_0 = a_0b_0$. Column $2^1$ has two bits, which a half adder (HA1) adds: the sum is $p_1$ and the carry $c_1$ goes to the next column. Column $2^2$ has $a_1b_1$ and $c_1$, which a second half adder (HA2) adds: the sum is $p_2$ and the carry is $p_3$.

$$p_0 = a_0b_0 \qquad p_1 = a_1b_0 \oplus a_0b_1$$

$$p_2 = a_1b_1 \oplus (a_1b_0 \cdot a_0b_1) \qquad p_3 = a_1b_1 \cdot a_1b_0 \cdot a_0b_1$$

 a1b0 a0b1        a0b0 ----------------------> p0
   \   /
   [HA1] --sum-----------------------------> p1
     | c1
 a1b1 +--> [HA2] --sum----------------------> p2
              \--carry---------------------> p3

The circuit needs 4 AND gates and 2 half adders. For $A = 11$ and $B = 11$ (that is $3 \times 3$), the four AND outputs are all 1. Then $p_0 = 1$, $p_1 = 0$ with $c_1 = 1$, $p_2 = 1 \oplus 1 = 0$ and $p_3 = 1$. The product is $1001 = 9$.

Flowchart for division of signed magnitude numbers. The sign and the magnitude are handled separately. The dividend is in $A$ and $Q$ joined, the divisor is in $B$, and the sign bits are $A_s$, $B_s$ and $Q_s$.

 START
   |
 Qs = As xor Bs ; SC = n-1
   |
 EA = A + (not B) + 1       (try A - B)
   |
 E = 1 ?--yes--> DIVIDE OVERFLOW (stop)
   | no
 shift left AQ ; EA = A + (not B) + 1
   |
 E = 1 ? --yes--> Qn = 1 ; A = EA
   | no
 Qn = 0   (A stays, so no restore needed)
   |
 SC = SC - 1 ; SC = 0 ? --no--> back to shift
   | yes
 END : Q = quotient, A = remainder

The first subtraction checks that the quotient fits in $n$ bits. If $A \ge B$ already, the divide overflows. After that, each cycle shifts left, subtracts $B$ by adding its 2's complement, and checks the carry $E$. A carry of 1 means the subtraction succeeded, so the quotient bit is 1 and $A$ takes the new value. A carry of 0 means it failed, so the quotient bit is 0 and $A$ keeps its old value. After $n-1$ cycles $Q$ holds the quotient and $A$ the remainder. The quotient sign is $A_s \oplus B_s$, and the remainder takes the sign of the dividend.

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